M41ST95WMX6 STMicroelectronics, M41ST95WMX6 Datasheet
M41ST95WMX6
Specifications of M41ST95WMX6
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M41ST95WMX6 Summary of contents
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FEATURES SUMMARY 5.0 OR 3.0V OPERATING VOLTAGE SERIAL PERIPHERAL INTERFACE (SPI) NVRAM SUPERVISOR FOR EXTERNAL LPSRAM 2.5 TO 5.5V OSCILLATOR OPERATING VOLTAGE AUTOMATIC SWITCH-OVER AND DESELECT CIRCUITRY CHOICE OF POWER-FAIL DESELECT VOLTAGES: – M41ST95Y 4.5 to 5.5V CC ...
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M41ST95Y*, M41ST95W TABLE OF CONTENTS FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table 7. Reset AC Characteristics ...
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M41ST95Y*, M41ST95W SUMMARY DESCRIPTION The M41ST95Y/W Serial TIMEKEEPER is a low power, 512-bit static CMOS SRAM orga- nized as 64 words by 8 bits. A built-in 32,768Hz oscillator (external crystal controlled) and 8 bytes of the SRAM (see Table 4., ...
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Figure 3. Logic Diagram ( BAT E SCL SDI EX M41ST95Y/W RSTIN1 RSTIN2 WDI PFI V SS Note: 1. For SOX28 package only. 2. Open drain 3. Available only in 28-pin, 300mil SOIC (MX) package. Table 1. ...
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M41ST95Y*, M41ST95W Figure 4. 28-pin SOIC Connections SQW M41ST95Y 22 M41ST95W WDI 8 21 RSTIN1 9 20 RSTIN2 ...
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Figure 6. Block Diagram E SDO SPI INTERFACE SDI SCL 32kHz Crystal OSCILLATOR WDI BAT RSTIN1 RSTIN2 EX PFI 1.25V (Internal) Note: 1. Open Drain Output 2. Available only in 28-pin, 300mil SOIC (MX) package. REAL TIME ...
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M41ST95Y*, M41ST95W Figure 7. Hardware Hookup D SPI Interface with (CPOL, CPHA) ( ('0','0') or ('1','1') C Master (ST6, ST7, ST9, ST10, Others) CS3 CS2 CS1 Note: 1. CPOL (Clock Polarity) and CPHA (Clock Phase) are bits that ...
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OPERATION The M41ST95Y/W clock operates as a slave de- vice on the SPI serial bus. Each memory device is accessed by a simple serial interface that is SPI bus compatible. The bus signals are SCL, SDI and SDO (see Table ...
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M41ST95Y*, M41ST95W Signal Description Serial Data Output (SDO). The output pin is used to transfer data serially out of the Memory. Data is shifted out on the falling edge of the serial clock. Serial Data Input (SDI). The input pin ...
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Figure 9. Input Timing Requirements E SCL tDVCH MSB IN SDI HIGH IMPEDANCE SDO Figure 10. Output Timing Requirements E SCL tCLQV tCLQX MSB OUT SDO ADDR. LSB IN SDI Figure 11. WRITE Cycle Timing: RTC and External SRAM Control ...
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M41ST95Y*, M41ST95W Table 3. AC Characteristics Symbol f Serial Clock Input Frequency SCL (2) Clock High t CH (3) Clock Transition (Fall Time) t CHCL t Serial Clock Input High to Input Data Transition CHDX t Serial Clock Input High ...
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READ and WRITE Cycles Address and data are shifted MSB first into the Se- rial Data Input (SDI) and out of the Serial Data Output (SDO). Any data transfer considers the first bit to define whether a READ or WRITE ...
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M41ST95Y*, M41ST95W Figure 13. WRITE Mode Sequence SCL 7 BIT ADDR W/R BIT SDI MSB SDO Data Retention Mode With valid V applied, the M41ST95Y/W can be CC accessed as described ...
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CLOCK OPERATION The eight byte clock register (see 4., page 16) is used to both set the clock and to read the date and time from the clock binary coded decimal format. Tenths/Hundredths of Sec- onds, Seconds, Minutes, ...
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M41ST95Y*, M41ST95W ® Table 4. TIMEKEEPER Register Map Addr 00h 0.1 Seconds 01h ST 10 Seconds 02h 0 10 Minutes 03h CEB CB 04h TR 0 05h 0 0 06h 0 0 07h 10 Years 08h OUT ...
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Calibrating the Clock The M41ST95Y/W is driven by a quartz-controlled oscillator with a nominal frequency of 32,768Hz. Uncalibrated clock accuracy will not exceed ±35 ppm (parts per million) oscillator frequency error at 25°C, which equates to about ±1.53 minutes per ...
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M41ST95Y*, M41ST95W To disable the alarm, write '0' to the Alarm Date Register and to RPT1-5. The IRQ/FT/OUT output is cleared by a READ to the Flags Register as shown in Figure 14. A subsequent READ of the Flags Register ...
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Figure 15. Back-up Mode Alarm Waveforms PFD V SO ABE, AFE Bits in Interrupt Register AF bit in Flags Register IRQ/FT/OUT Watchdog Timer The watchdog timer can be used to detect an out- of-control microprocessor. The user ...
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M41ST95Y*, M41ST95W Square Wave Output The M41ST95Y/W offers the user a programma- ble square wave function which is output on the SQW pin. RS3-RS0 bits located in 13h establish the square wave output frequency. These fre- quencies are listed in ...
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Power-on Reset The M41ST95Y/W continuously monitors V When V falls to the power fail detect trip point, CC the RST pulls low (open drain) and remains low on power-up for t after V passes V REC CC The RST pin ...
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M41ST95Y*, M41ST95W Power-fail INPUT/OUTPUT The Power-Fail Input (PFI) is compared to an in- ternal reference voltage (1.25V). If PFI is less than the power-fail threshold (V PFI Output (PFO) will go low. This function is intended for use as an ...
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Century Bit Bits D7 and D6 of Clock Register 03h contain the CENTURY ENABLE Bit (CEB) and the CENTURY Bit (CB). Setting CEB to a '1' will cause CB to tog- gle, either from a '0' to '1' or from ...
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M41ST95Y*, M41ST95W Figure 18. Crystal Accuracy Across Temperature Frequency (ppm –20 –40 –60 –80 –100 –120 –140 –160 –40 –30 –20 Figure 19. Calibration Waveform NORMAL POSITIVE CALIBRATION NEGATIVE CALIBRATION 24/ – T ...
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... CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode. CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets. not implied. Exposure to Absolute Maximum Rat- ing conditions for extended periods may affect de- vice reliability. STMicroelectronics SURE Program and other rel- evant quality documents. Parameter Off, Oscillator Off) CC M41ST95Y ...
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M41ST95Y*, M41ST95W DC AND AC PARAMETERS This section summarizes the operating and mea- surement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests ...
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Table 13. DC Characteristics Sym Parameter Battery Current OSC ON (2) I BAT Battery Current OSC OFF I Supply Current CC1 Supply Current I CC2 (Standby) Input Leakage Current ( Input Leakage Current (PFI) Output Leakage (4) I ...
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M41ST95Y*, M41ST95W Figure 21. Power Down/Up Mode AC Waveforms PFD (max) V PFD (min tPD PFO INPUTS RECOGNIZED RST OUTPUTS VALID (PER CONTROL INPUT) E CON Table 14. Power Down/Up AC Characteristics Symbol (2) ...
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PACKAGE MECHANICAL INFORMATION Figure 22. SOH28 – 28-lead Plastic Small Outline, Battery SNAPHAT, Package Outline SOH-A Note: Drawing is not to scale. Table 15. SOH28 – 28-lead Plastic Small Outline, battery SNAPHAT, Package Mechanical Data ...
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M41ST95Y*, M41ST95W Figure 23. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Outline Note: Drawing is not to scale. Table 16. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Mechanical Data Symbol Typ A ...
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Figure 24. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Outline Note: Drawing is not to scale. Table 17. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Mech. Data Symbol Typ ...
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M41ST95Y*, M41ST95W Figure 25. SOX28 – 28-lead Plastic Small Outline, 300mils, Embedded Crystal, Outline SO-E Note: Drawing is not to scale. Table 18. SOX28 – 28-lead Plastic Small, 300mils, Embedded Crystal, Package Mech. Data ...
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PART NUMBERING Table 19. Ordering Information Scheme Example: Device Type M41ST Supply Voltage and Write Protect Voltage (1) 95Y = V = 4.5 to 5.5V; 4.20V CC 95W = V = 2.7 to 3.6V; 2.55V CC Package (1, ...
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M41ST95Y*, M41ST95W REVISION HISTORY Table 21. Document Revision History Date Rev. # February 2002 1.0 First draft 27-Mar-02 1.1 Change t 01-Apr-02 1.2 Addition of new package option and inherent features 12-Apr-02 2.0 Document promoted Add marketing note; (Figure 1); ...
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... No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics ...