DP8572AN National Semiconductor, DP8572AN Datasheet - Page 10

IC REAL TIME CLOCK W/RAM 24 DIP

DP8572AN

Manufacturer Part Number
DP8572AN
Description
IC REAL TIME CLOCK W/RAM 24 DIP
Manufacturer
National Semiconductor
Type
Clock/Calendar/NVSRAMr
Datasheet

Specifications of DP8572AN

Memory Size
44B
Time Format
HH:MM:SS:hh (12/24 hr)
Date Format
YY-MM-DD-dd
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Through Hole
Package / Case
24-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
*DP8572AN
DP8572

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0
Functional Description
The oscillator is programmed via the Real Time Mode Reg-
ister to operate at various frequencies The crystal oscillator
is designed to offer optimum performance at each frequen-
cy Thus at 32 768 kHz the oscillator is configured as a low
frequency and low power oscillator At the higher frequen-
cies the oscillator inverter is reconfigured In addition to the
inverter the oscillator feedback bias resistor is included on
chip as shown in Figure 4 The oscillator input may be driv-
en from an external source if desired Refer to test mode
application note for details The oscillator stability is en-
hanced through the use of an on chip regulated power sup-
ply
The typical range of trimmer capacitor (as shown in Oscilla-
tor Circuit Diagram Figure 4 and in the typical application) at
the oscillator input pin is suggested only to allow accurate
tuning of the oscillator This range is based on a typical
printed circuit board layout and may have to be changed
depending on the parasitic capacitance of the printed circuit
board or fixture being used In all cases the load capaci-
tance specified by the crystal manufacturer (nominal value
11 pF for the 32 768 crystal) is what determines proper os-
cillation This load capcitance is the series combination of
capacitance on each side of the crystal (with respect to
ground)
32 32 768 kHz 47 pF
4 194304 MHz
4 9152 MHz
XTAL
FIGURE 4 Oscillator Circuit Diagram
68 pF
68 pF 29 pF–49 pF 500
C
o
2 pF–22 pF
0 pF–80 pF
C
t
(Continued)
150 k
500
Internally)
(Switched
R
to 900
to 900
OUT
to 350 k
TL F 9980–9
10
Figure 5 )
INTERRUPT LOGIC FUNCTIONAL DESCRIPTION
The RTC has the ability to coordinate processor timing ac-
tivities To enhance this an interrupt structure has been im-
plemented which enables several types of events to cause
interrupts Interrupts are controlled via two Control Regis-
ters in block 1 and two Status Registers in block 0 (See
Register Description for notes on paging and also Figure 5
and Table I )
The interrupts are enabled by writing a one to the appropri-
ate bits in Interrupt Control Register 0 and or 1
The Interrupt Status Flag D0 in the Main Status Register
indicates the state of INTR and MFO outputs It is set when
either output becomes active and is cleared when all RTC
interrupts have been cleared and no further interrupts are
pending (i e both INTR and MFO are returned to their inac-
tive state) This flag enables the RTC to be rapidly polled by
the P to determine the source of an interrupt in a wired
OR interrupt system (The Interrupt Status Flag provides a
true reflection of all conditions routed to the external pins )
Status for the interrupts are provided by the Main Status
Register and the Periodic Flag Register Bits D1– D5 of the
Main Status Register are the main interrupt bits
These register bits will be set when their associated timing
events occur Enabled Alarm comparisons that occur will
set its Main Status Register bit to a one However an exter-
nal interrupt will only be generated if the Alarm interrupt
enable bit is set (see Figure 5 )
Disabling the periodic interrupts will mask the Main Status
Register periodic bit but not the Periodic Flag Register bits
The Power Fail Interrupt bit is set when the interrupt is en-
abled and a power fail event has occurred and is not reset
until the power is restored If all interrupt enable bits are 0
no interrupt will be asserted However status still can be
read from the Main Status Register in a polled fashion (see
To clear a flag in bits D2 and D3 of the Main Status Register
a 1 must be written back into the bit location that is to be
cleared For the Periodic Flag Register reading the status
will reset all the periodic flags
Main Status Register
Periodic Flag Register
Interrupt Control
Interrupt Control
Output Mode
Register 0
Register 1
Register
Register Name
Applicable to Interrupt Control
TABLE I Registers that are
Register
Select
X
0
1
1
1
Select
Page
X
0
0
0
0
Address
00H
03H
03H
04H
02H