DP8572AN National Semiconductor, DP8572AN Datasheet



Manufacturer Part Number
National Semiconductor

Specifications of DP8572AN

Memory Size
Time Format
HH:MM:SS:hh (12/24 hr)
Date Format
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Through Hole
Package / Case
24-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names

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Part Number
Bonase Electronics (HK) Co., Limited Bonase Electronics (HK) Co., Limited
Part Number:
6 219
C 1995 National Semiconductor Corporation
DP8572A DP8572AM Real Time Clock (RTC)
General Description
The DP8572A (8572AM militarized version) is intended for
use in microprocessor based systems where information is
required for multi-tasking data logging or general time of
day date information This device is implemented in low
voltage silicon gate microCMOS technology to provide low
standby power in battery back-up environments The cir-
cuit’s architecture is such that it looks like a contiguous
block of memory or I O ports The address space is orga-
nized as 2 software selectable pages of 32 bytes This in-
cludes the Control Registers the Clock Counters the Alarm
Compare RAM and the Time Save RAM Any of the RAM
locations that are not being used for their intended purpose
may be used as general purpose CMOS RAM
Time and date are maintained from 1 100 of a second to
year and leap year in a BCD format 12 or 24 hour modes
Day of week day of month and day of year counters are
provided Time is controlled by an on-chip crystal oscillator
requiring only the addition of the crystal and two capacitors
The choice of crystal frequency is program selectable
Power failure logic and control functions have been integrat-
ed on chip This logic is used by the RTC to issue a power
fail interrupt and lock out the p interface The time power
fails may be logged into RAM automatically when V
Block Diagram
TRI-STATE is a registered trademark of National Semiconductor Corporation
TL F 9980
BB l
the main supply to the battery supply Status bits are provid-
ed to indicate initial application of battery power system
power and low battery detect
BB l
Full function real time clock calendar
Power fail features
On-chip interrupt structure
Up to 44 bytes of CMOS RAM
MIL-STD-883C compliant
12 24 hour mode timekeeping
Day of week and day of years counters
Four selectable oscillator frequencies
Parallel resonant oscillator
Internal power supply switch to external battery
Power Supply Bus glitch protection
Automatic log of time into RAM at power failure
Periodic alarm and power fail interrupts
Additionally two supply pins are provided When
5962-91641-01MJX (future)
internal circuitry will automatically switch from
RRD-B30M75 Printed in U S A
TL F 9980 – 1
May 1993

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DP8572AN Summary of contents

Page 1

... This logic is used by the RTC to issue a power fail interrupt and lock out the p interface The time power fails may be logged into RAM automatically when V Block Diagram TRI-STATE is a registered trademark of National Semiconductor Corporation C 1995 National Semiconductor Corporation TL F 9980 V ...

Page 2

Absolute Maximum Ratings Specifications for the 883 version of this product are listed separately Supply Voltage ( Input Voltage ( Output Voltage ( ...

Page 3

AC Electrical Characteristics PFAIL Symbol READ TIMING t Address Valid Prior to Read Strobe AR t Read Strobe Width (Note Chip Select to Data ...

Page 4

... Absolute Maximum Ratings The 883 specifications are written to reflect the current (at the time of printing) Rel Electrical Test Specifica- tions (RETS) established by National Semiconductor for this product For a copy of the latest version of the RETS please contact your local National Semiconduc- tor sales office or distributor ...

Page 5

Military Version AC Electrical Characteristics and PFAIL Symbol READ TIMING t Address Valid Prior to Read Strobe AR t Read Strobe Width (Note ...

Page 6

Timing Waveforms Read Timing Diagram Write Timing Diagram 9980 – 9980 – 4 ...

Page 7

... This is the main system power pin CC GND This is the common ground power pin for both V and V CC Connection Diagrams Dual-In-Line P control Order Number DP8572AN or DP8572AMD 883 See NS Package Number D24C or N24C Plastic Chip Carrier The BB Top View Order Number DP8572AV See NS Package Number V28A ...

Page 8

Functional Description The DP8572A contains a fast access real time clock inter- rupt control logic power fail detect logic and CMOS RAM All functions of the RTC are controlled by a set of seven registers A simplified block diagram that ...

Page 9

Functional Description (Continued) INITIAL POWER-ON of BOTH V and and V may be applied in any sequence In order for BB CC the power fail circuitry to function correctly whenever power is off the V pin ...

Page 10

Functional Description (Continued) The oscillator is programmed via the Real Time Mode Reg- ister to operate at various frequencies The crystal oscillator is designed to offer optimum performance at each frequen- cy Thus at 32 768 kHz the oscillator is ...

Page 11

Functional Description (Continued) Interrupts Fall Into Three Categories 1 The Alarm Compare Interrupt Issued when the value in the time compared RAM equals the counter 2 The Periodic Interrupts These are issued at every incre- ment of the specific clock ...

Page 12

Functional Description (Continued) 12 ...

Page 13

Functional Description (Continued) FIGURE 6 System-Battery Switchover (Upper Left) Power Fail If chip select is low when a power failure is detected a safety circuit will ensure that if a read or write is held active continuously for greater than ...

Page 14

Functional Description (Continued) the chip is unlocked but only after another 30 s min 63 s max debounce time The system designer must en- sure that his system is stable when power has returned The power fail circuitry contains active ...

Page 15

Functional Description (Continued) MAIN STATUS REGISTER The Main Status Register is always located at address 0 regardless of the register block or the page selected D0 This read only bit is a general interrupt status bit that is taken directly ...

Page 16

Functional Description (Continued) D5 The Delay Enable bit is used when a power fail occurs If this bit is set a 480 s delay is generated internally before the P interface is locked out This will enable the access the ...

Page 17

Functional Description (Continued) D7 This bit is used to program the signal appearing at the MFO output as follows D7 MFO Output Signal 0 Power Fail Interrupt 1 Buffered Crystal Oscillator INTERRUPT CONTROL REGISTER 0 D0 –D5 These bits are ...

Page 18

Control and Status Register Address Bit Map Main Status Register ADDRESS Page Register RAM Select Select Periodic Flag Register ...

Page 19

Application Hints Suggested Initialization Procedure for DP8572A in Battery Backed Applications that use the V Pin BB 1 Enter the test mode by writing bit D7 in the Period- ic Flag Register 2 Write zero to the ...

Page 20

Typical Performance Characteristics Operating Current vs Supply Voltage (Single Supply Mode F 32 768 kHz) e OSC Standby Current vs Power Supply Voltage (F 32 768 kHz) e OSC Operating Current vs Supply Voltage (Battery Backed Mode F 32 768 ...

Page 21

... Physical Dimensions inches (millimeters) 24-Lead Hermetically Sealed Dual-In-Line Package (D) Order Number DP8572AMD 883 NS Package Number D24C Molded Dual-In-Line Package (N) Order Number DP8572AN NS Package Number N24C 21 ...

Page 22

... National Semiconductor National Semiconductor National Semiconductores Japan Ltd Hong Kong Ltd Do Brazil Ltda Sumitomo Chemical 13th Floor Straight Block ...

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