DP8572AN National Semiconductor, DP8572AN Datasheet - Page 7

IC REAL TIME CLOCK W/RAM 24 DIP

DP8572AN

Manufacturer Part Number
DP8572AN
Description
IC REAL TIME CLOCK W/RAM 24 DIP
Manufacturer
National Semiconductor
Type
Clock/Calendar/NVSRAMr
Datasheet

Specifications of DP8572AN

Memory Size
44B
Time Format
HH:MM:SS:hh (12/24 hr)
Date Format
YY-MM-DD-dd
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Through Hole
Package / Case
24-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
*DP8572AN
DP8572

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0
General Description
The DP8572A’s interrupt structure provides three basic
types of interrupts Periodic Alarm Compare and Power
Fail Interrupt mask and status registers enable the masking
and easy determination of each interrupt
Pin Description
CS RD WR (Inputs) These pins interface to
lines The CS pin is an active low enable for the read and
write operations Read and Write pins are also active low
and enable reading or writing to the RTC All three pins are
disabled when power failure is detected However if a read
or write is in progress at this time it will be allowed to com-
plete its cycle
A0 –A4 (Inputs) These 5 pins are for register selection
They individually control which location is to be accessed
These inputs are disabled when power failure is detected
OSC IN (Input) OSC OUT (Output) These two pins are
used to connect the crystal to the internal parallel resonant
oscillator The oscillator is always running when power is
applied to V
the Real Time Mode Register have been set
MFO (Output) The multi-function output can be used as a
second interrupt output for interrupting the P This pin can
also provide an output for the oscillator The MFO output is
configured as push-pull active high for normal or single
power supply operation and as an open drain during stand-
by mode (V
up resistor is attached it should be connected to a voltage
no greater than V
INTR (Output) The interrupt output is used to interrupt the
processor when a timing event or power fail has occurred
and the respective interrupt has been enabled The INTR
output is permanently configured active low open drain If in
battery backed mode and a pull-up resistor is attached it
should be connected to a voltage no greater than V
output is a DC voltage level To clear the INTR write a 1 to
the appropriate bit(s) in the Main Status Register
D0 –D7 (Input Output) These 8 bidirectional pins connect
to the host
write to the RTC When the PFAIL pin goes low and a write
is not in progress these pins are at TRI-STATE
PFAIL (Input) In battery backed mode this pin can have a
digital signal applied to it via some external power detection
logic When PFAIL
mode in a minimum of 30 s or a maximum of 63 s unless
lockout delay is programmed In the single power supply
mode this pin is not useable as an input and should be tied
to V
tion
V
up power supply This power supply is switched to the inter-
nal circuitry when the V
ing this pin eliminates the need for external logic to switch in
and out the back-up power supply If this feature is not to be
used then this pin must be tied to ground the RTC pro-
grammed for single power supply only and power applied to
the V
BB
CC
(Battery Power Pin) This pin is connected to a back-
CC
Refer to section on Power Fail Functional Descrip-
pin
BB l
BB
P’s data bus and are used to read from and
and V
V
BB
CC
e
CC
) If in battery backed mode and a pull-
logic 0 the RTC goes into a lockout
CC
and the correct crystal select bits in
becomes lower than V
(Continued)
BB
P control
BB
Utiliz-
The
7
V
GND This is the common ground power pin for both V
and V
Connection Diagrams
CC
This is the main system power pin
Order Number DP8572AN or DP8572AMD 883
CC
See NS Package Number D24C or N24C
See NS Package Number V28A
Order Number DP8572AV
Plastic Chip Carrier
Dual-In-Line
Top View
Top View
TL F 9980 – 5
TL F 9980 – 6
BB