DP8572AN National Semiconductor, DP8572AN Datasheet - Page 14

IC REAL TIME CLOCK W/RAM 24 DIP

DP8572AN

Manufacturer Part Number
DP8572AN
Description
IC REAL TIME CLOCK W/RAM 24 DIP
Manufacturer
National Semiconductor
Type
Clock/Calendar/NVSRAMr
Datasheet

Specifications of DP8572AN

Memory Size
44B
Time Format
HH:MM:SS:hh (12/24 hr)
Date Format
YY-MM-DD-dd
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Through Hole
Package / Case
24-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
*DP8572AN
DP8572

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DP8572AN
Quantity:
6 219
Company:
Part Number:
DP8572AN
Manufacturer:
ADI
Quantity:
89
Company:
Part Number:
DP8572AN
Manufacturer:
ADI
Quantity:
89
Company:
Part Number:
DP8572AN
Manufacturer:
ADI
Quantity:
89
Company:
Part Number:
DP8572AN
Manufacturer:
ADI
Quantity:
89
Company:
Part Number:
DP8572AN,,800,HARRIS,DIP,,,,18+
0
Functional Description
the chip is unlocked but only after another 30 s min
63
sure that his system is stable when power has returned
The power fail circuitry contains active linear circuitry that
draws supply current from V
undesirable so this circuit can be disabled by masking the
power fail interrupt The power fail input can perform all
lock-out functions previously mentioned except that no ex-
ternal interrupt will be issued Note that the linear power fail
circuitry is switched off automatically when using V
standby mode
LOW BATTERY INITIAL POWER ON DETECT AND
POWER FAIL TIME SAVE
There are three other functions provided on the DP8572A to
ease power supply control These are an initial Power On
detect circuit which also can be used as a time keeping
failure detect a low battery detect circuit and a time save
on power failure
On initial power up the Oscillator Fail Flag will be set to a
one and the real time clock start bit reset to a zero This
indicates that an oscillator fail event has occurred and time
keeping has failed
The Oscillator Fail flag will not be reset until the real-time
clock is started This allows the system to discriminate be-
tween an initial power-up and recovery from a power failure
If the battery backed mode is selected then bit D6 of the
Periodic Flag Register must be written low This will not af-
fect the contents of the Oscillator Fail Flag
Another status bit is the low battery detect This bit is set
only when the clock is operating under the V
when the battery voltage is determined to be less than 2 1V
(typical) When the power fail interrupt enable bit is low it
disables the power fail circuit and will also shut off the low
battery voltage detection circuit as well
To relieve CPU overhead for saving time upon power failure
the Time Save Enable bit is provided to do this automatical-
ly (See also Reading the Clock Latched Read ) The Time
Save Enable bit when set causes the Time Save RAM to
follow the contents of the clock This bit can be reset by
software but if set before a power failure occurs it will auto-
matically be reset when the clock switches to the battery
supply (not when a power failure is detected by the PFAIL
pin) Thus writing a one to the Time Save bit enables both a
software write or power fail write
SINGLE POWER SUPPLY APPLICATIONS
The DP8572A can be used in a single power supply applica-
tion To achieve this the V
ground and the power connected to V
The Oscillator Failed Single Supply bit in the Periodic Flag
Register should be set to a logic 1 which will disable the
oscillator battery reference circuit The power fail interrupt
should also be disabled This will turn off the linear power
fail detection circuits and will eliminate any quiescent power
drawn through these circuits Until the crystal select bits are
initialized the DP8572A may consume about 50 A due to
arbitrary oscillator selection at power on
(This extra 50
mode is selected)
DETAILED REGISTER DESCRIPTION
There are 5 external address bits Thus the host microproc-
essor has access to 28 locations at one time An internal
switching scheme provides a total of 61 locations
s max debounce time The system designer must en-
A is not consumed if the battery backed
CC
BB
In some cases this may be
pin must be connected to
(Continued)
CC
and PFAIL pins
CC
pin and
BB
in
14
This complete address space is organized into two pages
Page 0 contains two blocks of control registers timers real
time clock counters and special purpose RAM while page
1 contains general purpose RAM Using two blocks enables
the 9 control registers to be mapped into 5 locations The
only register that does not get switched is the Main Status
Register It contains the page select bit and the register
select bit as well as status information
A memory map is shown in Figure 2 and register addressing
in Table III They show the name address and page loca-
tions for the DP8572A
Note 1 PS Page Select (Bit D7 of Main Status Register)
Note 2 RS Register Select (Bit D6 of Main Status Register)
Note 3 The LSB counters count 0
reaches 3 Then the LSB counters count to 65 or 66 (if a leap year) The
rollover is from 365 366 to 1
01 –1F
A0-4
CONTROL REGISTERS
COUNTERS (CLOCK CALENDAR)
TIME COMPARE RAM
TIME SAVE RAM
0A
0B
0C
0D
0E
1A
1B
1C
1D
1E
00
03
04
01
02
03
04
05
06
07
08
09
13
14
15
16
17
18
19
1F
(Note 1) (Note 2)
PS
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
TABLE III Register Counter RAM
Addressing for DP8572A
RS
X
0
0
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
X
X
Main Status Register
Periodic Flag Register
Time Save Control Register
Real Time Mode Register
Output Mode Register
Interrupt Control Register 0
Interrupt Control Register 1
1 100 1 10 Seconds (0 –99)
Seconds
Minutes
Hours
Days of
Months
Years
Julian Date (LSB)
Julian Date
Day of Week
Sec Compare RAM
Min Compare RAM
Hours Compare
DOM Compare
Months Compare
DOW Compare RAM (1 –7)
Seconds Time Save RAM
Minutes Time Save RAM
Hours Time Save RAM
Day of Month Time Save RAM
Months Time Save RAM
RAM
RAM Test Mode Register
2nd Page General Purpose RAM
Month
RAM
RAM
RAM
99 until the hundreds of days counter
Description
(0 – 59)
(0 – 59)
(1 –12 0 – 23)
(1 –12)
(0 –99)
(0 –99) (Note 3)
(0 –3)
(1 –7)
(0 –59)
(0 –59)
(1 –12 0 –23)
(1 –12)
(1 – 28 29 30 31)
(1 –28 29 30 31)