MAX5865ETM+ Maxim Integrated Products, MAX5865ETM+ Datasheet - Page 24

• Manufacturer Part Number: MAX5865ETM+
• Description: IC ANLG FRONT END 40MSPS 48-TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX5865ETM+

• Number Of Bits: 10
• Number Of Channels: 4
• Power (watts): 2.10W
• Voltage - Supply, Analog: 2.7 V ~ 3.3 V
• Voltage - Supply, Digital: 1.8 V ~ 3.3 V
• Package / Case: 48-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Ultra-Low-Power, High-Dynamic-
Performance, 40Msps Analog Front End
Power-supply rejection is defined as the shift in offset
and gain error when the power supply is changed ±5%.
A small -20dBFS analog input signal is applied to an
ADC in such a way that the signal’s slew rate does not
limit the ADC’s performance. The input frequency is
then swept up to the point where the amplitude of the
digitized conversion result has decreased by 3dB. Note
that the T/H performance is usually the limiting factor
for the small-signal input bandwidth.
A large -0.5dBFS analog input signal is applied to an
ADC, and the input frequency is swept up to the point
where the amplitude of the digitized conversion result
has decreased by 3dB. This point is defined as the full-
power bandwidth frequency.
THD is the ratio of the RMS sum of the output harmonics
up to the Nyquist frequency divided by the fundamental:
where V
V
up to the Nyquist frequency.
Spurious-free dynamic range (SFDR) is the ratio of RMS
amplitude of the fundamental (maximum signal compo-
nent) to the RMS value of the next-largest distortion
component up to the Nyquist frequency excluding DC.
24
n
are the amplitudes of the 2nd through nth harmonic
______________________________________________________________________________________
1
DAC Dynamic Parameter Definitions
is the fundamental amplitude and V
THD
=
20log
Spurious-Free Dynamic Range




(V + V + ...+ V )
Total Harmonic Distortion
2
2
Power-Supply Rejection
Small-Signal Bandwidth
Full-Power Bandwidth
3
2
V
1
n
2




2
through
TRANSISTOR COUNT: 16,765
PROCESS: CMOS
TOP VIEW
REFP
GND
GND
GND
CLK
QA+
V
V
V
QA-
IA+
IA-
DD
DD
DD
10
11
12
1
2
3
4
5
6
7
8
9
MAX5865
QFN
Pin Configuration
Chip Information
36
35
34
33
32
31
30
29
28
27
26
25
CS
SCLK
DIN
V
DD9
DD8
DD7
DD6
DD5
DD4
DD3
DD2
DD