MAX5865ETM+ Maxim Integrated Products, MAX5865ETM+ Datasheet - Page 5

• Manufacturer Part Number: MAX5865ETM+
• Description: IC ANLG FRONT END 40MSPS 48-TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX5865ETM+

• Number Of Bits: 10
• Number Of Channels: 4
• Power (watts): 2.10W
• Voltage - Supply, Analog: 2.7 V ~ 3.3 V
• Voltage - Supply, Digital: 1.8 V ~ 3.3 V
• Package / Case: 48-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ELECTRICAL CHARACTERISTICS (continued)
(V
DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, C
otherwise noted. Typical values are at T
DAC ANALOG OUTPUT
Full-Scale Output Voltage
Output Common-Mode Range
ADC-DAC INTERCHANNEL CHARACTERISTICS
ADC-DAC Isolation
ADC-DAC TIMING CHARACTERISTICS
CLK Rise to I-ADC Channel-I
Output Data Valid
CLK Fall to Q-ADC Channel-Q
Output Data Valid
I-DAC Data to CLK Fall Setup
Time
Q-DAC Data to CLK Rise Setup
Time
CLK Fall to I-DAC Data Hold Time
C LK Ri se to Q- D AC D ata H ol d Ti m e
Clock Duty Cycle
CLK Duty-Cycle Variation
Digital Output Rise/Fall Time
SERIAL INTERFACE TIMING CHARACTERISTICS
Falling Edge of CS to Rising Edge
of First SCLK Time
DIN to SCLK Setup Time
DIN to SCLK Hold Time
SCLK Pulse Width High
SCLK Pulse Width Low
SCLK Period
SCLK to CS Setup Time
CS High Pulse Width
MODE RECOVERY TIMING CHARACTERISTICS
Shutdown Wake-Up Time
DD
= 3V, OV
PARAMETER
DD
= 1.8V, internal reference (1.024V), C
_______________________________________________________________________________________
Performance, 40Msps Analog Front End
SYMBOL
t
A
WAKE,SD
t
t
t
= +25°C, unless otherwise noted.) (Note 1)
t
t
t
DOQ
t
t
DHQ
CSW
V
DSQ
t
t
CSS
t
t
t
t
DOI
DSI
DHI
DH
CH
DS
CL
CP
CS
FS
Ultra-Low-Power, High-Dynamic-
ADC f
f
Figure 3 (Note 4)
Figure 3 (Note 4)
Figure 4 (Note 4)
Figure 4 (Note 4)
Figure 4 (Note 4)
Figure 4 (Note 4)
20% to 80%
Figure 5 (Note 4)
Figure 5 (Note 4)
Figure 5 (Note 4)
Figure 5 (Note 4)
Figure 5 (Note 4)
Figure 5 (Note 4)
Figure 5 (Note 4)
Figure 5 (Note 4)
From shutdown to Rx mode, Figure 6, ADC
settles to within 1dB
From shutdown to Tx mode, Figure 6, DAC
settles to within 10 LSB error
OUTQ
L
≈ 10pF on all digital outputs, f
INI
= 2.2MHz, f
= f
INQ
CONDITIONS
= 5.5MHz, DAC f
CLK
= 40MHz
REFP
OUTI
CLK
= C
=
= 40MHz, ADC input amplitude = -0.5dBFS,
REFN
= C
1.29
MIN
10
10
10
10
25
25
50
80
COM
0
0
0
0
= 0.33µF, Xcvr mode, unless
±400
TYP
±15
7.4
6.9
2.6
75
50
20
40
MAX
1. 5
9
9
UNITS
mV
dB
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
%
%
V
5