AD7476ARTZ-500RL7 Analog Devices Inc, AD7476ARTZ-500RL7 Datasheet - Page 16

• Manufacturer Part Number: AD7476ARTZ-500RL7
• Description: IC ADC 12BIT 1MSPS SOT-23-6
• Manufacturer: Analog Devices Inc

Specifications of AD7476ARTZ-500RL7

• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Design Resources: Output Channel Monitoring Using AD5380 (CN0008) AD5382 Channel Monitor Function (CN0012) AD5381 Channel Monitor Function (CN0013) AD5383 Channel Monitor Function (CN0015) AD5390/91/92 Channel Monitor Function (CN0030) Power off protected data acquisition signal chain using ADG4612 , AD711, and AD7476 (CN0165)
• Number Of Bits: 12
• Sampling Rate (per Second): 1M
• Number Of Converters: 1
• Power Dissipation (max): 17.5mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: SOT-23-6
• Resolution (bits): 12bit
• Sampling Rate: 1MSPS
• Input Channel Type: Single Ended
• Supply Voltage Range - Analog: 2.7V To 5.25V
• Supply Current: 3.5mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7476ACBZ - BOARD EVALUATION FOR AD7476AAD7476-DBRD - BOARD EVAL FOR AD7476AD7476A-DBRD - BOARD EVAL FOR AD7476A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: AD7476ARTZ-500RL7TR

AD7476/AD7477/AD7478
MICROPROCESSOR INTERFACING
The serial interface on the AD7476/AD7477/AD7478 allows
the part to be directly connected to a range of many different
microprocessors. This section explains how to interface the
AD7476/AD7477/AD7478 with some of the more common
microcontroller and DSP serial interface protocols.
AD7476/AD7477/AD7478 to TMS320C5x/C54x Interface
The serial interface on the TMS320C5x uses a continuous serial
clock and frame synchronization signals to synchronize the data
transfer operations with peripheral devices like the AD7476/
AD7477/AD7478. The CS input allows easy interfacing between
the TMS320C5x/C54x and the AD7476/AD7477/AD7478 without
any glue logic required. The serial port of the TMS320C5x/C54x
is set up to operate in burst mode with internal CLKX (Tx serial
clock) and FSX (Tx frame sync). The serial port control register
(SPC) must have the following setup: FO = 0, FSM = 1,
MCM = 1, and TXM = 1. The format bit, FO, may be set to 1
to set the word length to eight bits, in order to implement the
Power-Down mode on the AD7476/AD7477/AD7478. The
connection diagram is shown in Figure 18. It should be noted that
for signal processing applications, it is imperative that the frame
synchronization signal from the TMS320C5x/C54x provides
equidistant sampling.
AD7476/AD7477/AD7478 to ADSP-21xx Interface
The ADSP-21xx family of DSPs are interfaced directly to the
AD7476/AD7477/AD7478 without any glue logic required. The
SPORT control register should be set up as follows:
TFSW = RFSW = 1, Alternate Framing
INVRFS = INVTFS = 1, Active Low Frame Signal
DTYPE = 00, Right Justify Data
SLEN = 1111, 16-Bit Data-Words
ISCLK = 1, Internal Serial Clock
TFSR = RFSR = 1, Frame Every Word
IRFS = 0
ITFS = 1
Figure 18. Interfacing to the TMS320C5x/C54x
AD7478*
AD7476/
AD7477/
*ADDITIONAL PINS OMITTED FOR CLARITY
SDATA
SCLK
CS
CLKX
CLKR
DR
FSX
FSR
TMS320C54x*
TMS320C5x/
–16–
To implement the Power-Down mode, SLEN should be set
to 0111 to issue an 8-bit SCLK burst. The connection diagram
is shown in Figure 19. The ADSP-21xx has the TFS and RFS of
the SPORT tied together, with TFS set as an output and RFS
set as an input. The DSP operates in Alternate Framing mode
and the SPORT control register is set up as described. The
frame synchronization signal generated on the TFS is tied to
CS and as with all signal processing applications, equidistant
sampling is necessary. However, in this example, the timer
interrupt is used to control the sampling rate of the ADC and, under
certain conditions, equidistant sampling may not be achieved.
The timer registers, for example, are loaded with a value that will
provide an interrupt at the required sample interval. When an
interrupt is received, a value is transmitted with TFS/DT (ADC
control word). The TFS is used to control the RFS and therefore
the reading of data. The frequency of the serial clock is set in the
SCLKDIV register. When the instruction to transmit with TFS
is given (i.e., TX0 = AX0), the state of the SCLK is checked.
The DSP will wait until the SCLK has gone high, low, and high
before transmission will start. If the timer and SCLK values are
chosen such that the instruction to transmit occurs on or near
the rising edge of SCLK, the data may be transmitted, or it may
wait until the next clock edge.
For example, the ADSP-2111 has a master clock frequency of
16 MHz. If the SCLKDIV register is loaded with the value 3,
a SCLK of 2 MHz is obtained, and eight master clock periods
will elapse for every one SCLK period. If the timer registers
are loaded with the value 803, 100.5 SCLKs will occur between
interrupts and subsequently between transmit instructions. This
situation will result in nonequidistant sampling as the transmit
instruction is occurring on an SCLK edge. If the number of
SCLKs between interrupts is a whole integer figure of N, equidis-
tant sampling will be implemented by the DSP.
Figure 19. Interfacing to the ADSP-21xx
AD7478*
AD7476/
AD7477/
*ADDITIONAL PINS OMITTED FOR CLARITY
SDATA
SCLK
CS
SCLK
DR
RFS
TFS
ADSP-21xx*
REV. D