AD7476ARTZ-500RL7 Analog Devices Inc, AD7476ARTZ-500RL7 Datasheet - Page 2

• Manufacturer Part Number: AD7476ARTZ-500RL7
• Description: IC ADC 12BIT 1MSPS SOT-23-6
• Manufacturer: Analog Devices Inc

Specifications of AD7476ARTZ-500RL7

• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Design Resources: Output Channel Monitoring Using AD5380 (CN0008) AD5382 Channel Monitor Function (CN0012) AD5381 Channel Monitor Function (CN0013) AD5383 Channel Monitor Function (CN0015) AD5390/91/92 Channel Monitor Function (CN0030) Power off protected data acquisition signal chain using ADG4612 , AD711, and AD7476 (CN0165)
• Number Of Bits: 12
• Sampling Rate (per Second): 1M
• Number Of Converters: 1
• Power Dissipation (max): 17.5mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: SOT-23-6
• Resolution (bits): 12bit
• Sampling Rate: 1MSPS
• Input Channel Type: Single Ended
• Supply Voltage Range - Analog: 2.7V To 5.25V
• Supply Current: 3.5mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7476ACBZ - BOARD EVALUATION FOR AD7476AAD7476-DBRD - BOARD EVAL FOR AD7476AD7476A-DBRD - BOARD EVAL FOR AD7476A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: AD7476ARTZ-500RL7TR

AD7476–SPECIFICATIONS
Parameter
DYNAMIC PERFORMANCE
DC ACCURACY
ANALOG INPUT
LOGIC INPUTS
LOGIC OUTPUTS
CONVERSION RATE
POWER REQUIREMENTS
NOTES
1
2
3
4
Temperature ranges as follows: A, B Versions: –40°C to +85°C; S Version: –55°C to +125°C.
Operational from V
See Terminology section.
Maximum B, S version specifications apply as typical figures when V
Signal-to-(Noise + Distortion) (SINAD)
Signal-to-Noise Ratio (SNR)
Total Harmonic Distortion (THD)
Peak Harmonic or Spurious Noise (SFDR)
Intermodulation Distortion (IMD)
Aperture Delay
Aperture Jitter
Full Power Bandwidth
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Gain Error
Input Voltage Ranges
DC Leakage Current
Input Capacitance
Input High Voltage, V
Input Low Voltage, V
Input Current, I
Input Current, I
Input Capacitance, C
Output High Voltage, V
Output Low Voltage, V
Floating-State Leakage Current
Floating-State Output Capacitance
Output Coding
Conversion Time
Track-and-Hold Acquisition Time
Throughput Rate
V
I
Full Power-Down Mode
Power Dissipation
DD
DD
Second-Order Terms
Third-Order Terms
Normal Mode (Static)
Normal Mode (Operational)
Normal Mode (Operational)
Full Power-Down
3
3
IN
IN
DD
, SCLK Pin
, CS Pin
7
= 2.0 V.
3
IN
INL
INH
5
OL
OH
3
3
3
3
5
3
3
A Version
69
70
70
–80
–82
–78
–78
12
± 1
± 0.75
± 0.5
± 0.5
0 to V
± 1
2.4
1.8
0.4
0.8
± 1
± 1
10
V
0.4
± 10
10
350
2.35/5.25
2
1
3.5
1.6
1
80
4.8
5
3
10
30
6.5
30
0.8
500
1000
17.5
Straight (Natural) Binary
DD
– 0.2
DD
1, 2
1
(A Version: V
noted; S and B Versions: V
unless otherwise noted; T
B Version
70
71.5
71
72.5
–78
–80
–78
–78
10
30
6.5
12
± 1.5
± 0.6
–0.9/+1.5
± 0.75
± 1.5
± 1.5
0 to V
± 1
30
2.4
1.8
0.4
0.8
± 1
± 1
10
V
0.4
± 10
10
1.33
500
400
600
2.35/5.25
2
1
3
1.4
1
80
15
4.2
5
3
DD
DD
– 0.2
= 5.25 V.
DD
1, 2
–2–
DD
= 2.7 V to 5.25 V, f
S Version
69
70
70
–78
–80
–78
–78
10
30
6.5
12
± 1.5
± 0.6
–0.9/+1.5
± 0.75
± 2
± 2
0 to V
± 1
30
2.4
1.8
0.4
0.8
± 1
± 1
10
V
0.4
± 10
10
1.33
500
400
600
2.35/5.25
2
1
3
1.4
1
80
15
4.2
5
3
DD
– 0.2
5
6
7
Specifications subject to change without notice.
Guaranteed by characterization.
A Version: f
See Power vs. Throughput Rate section.
DD
1, 2
A
DD
= T
= 2.35 V to 5.25 V, f
Unit
dB min
dB min
dB typ
dB min
dB typ
dB typ
dB typ
dB typ
dB typ
ns typ
ps typ
MHz typ
Bits
LSB max
LSB typ
LSB max
LSB typ
LSB max
LSB typ
LSB max
LSB typ
V
µA max
pF typ
V min
V min
V max
V max
µA max
µA typ
pF max
V min
V max
µA max
pF max
µs max
ns max
ns max
kSPS max
V min/max
mA typ
mA typ
mA max
mA max
µA max
µA max
mW max
mW max
µW max
µW max
MIN
SAMPLE
to T
SCLK
MAX = 1 MSPS; B, S Versions: f
MAX
= 20 MHz, f
, unless otherwise noted.)
Test Conditions/Comments
f
B Version, V
T
B Version, V
fa = 103.5 kHz, fb = 113.5 kHz
fa = 103.5 kHz, fb = 113.5 kHz
@ 3 dB
S, B Versions, V
A Version, V
Guaranteed No Missed Codes to 12 Bits
V
V
V
Typically 10 nA, V
I
I
16 SCLK Cycles
Full-Scale Step Input
Sine Wave Input ≤100 kHz
See Serial Interface Section
Digital I/Ps = 0 V or V
V
V
V
V
SCLK Off
SCLK On
V
V
V
V
IN
SOURCE
SINK
DD
A
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
= 100 kHz Sine Wave
= 25°C
= 4.75 V to 5.25 V. SCLK On or Off
= 2.35 V to 3.6 V. SCLK On or Off
= 4.75 V to 5.25 V; f
= 2.35 V to 3.6 V; f
= 2.35 V
= 3 V
= 5 V
= 5 V; f
= 3 V; f
= 5 V; SCLK Off
= 3 V; SCLK Off
= 200 µA
SCLK
SAMPLE
= 200 µA; V
= 12 MHz, f
SAMPLE
SAMPLE
DD
DD
DD
= 1 MSPS, unless otherwise
= 2.4 V to 5.25 V
= 2.4 V to 5.25 V
= (2.7 V to 3.6 V)
DD
IN
DD
= (2.35 V to 3.6 V)
= f
= f
= 0 V or V
= 2.35 V to 5.25 V
DD
SAMPLE
SAMPLE
SAMPLE
SAMPLE
SAMPLE
SAMPLE
MAX
MAX
= 600 kSPS,
MAX = 600 kSPS.
= f
= f
DD
SAMPLE
SAMPLE
6
6
REV. D
4
MAX
;
MAX
6
6