AD7476ARTZ-500RL7 Analog Devices Inc, AD7476ARTZ-500RL7 Datasheet - Page 5

• Manufacturer Part Number: AD7476ARTZ-500RL7
• Description: IC ADC 12BIT 1MSPS SOT-23-6
• Manufacturer: Analog Devices Inc

Specifications of AD7476ARTZ-500RL7

• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Design Resources: Output Channel Monitoring Using AD5380 (CN0008) AD5382 Channel Monitor Function (CN0012) AD5381 Channel Monitor Function (CN0013) AD5383 Channel Monitor Function (CN0015) AD5390/91/92 Channel Monitor Function (CN0030) Power off protected data acquisition signal chain using ADG4612 , AD711, and AD7476 (CN0165)
• Number Of Bits: 12
• Sampling Rate (per Second): 1M
• Number Of Converters: 1
• Power Dissipation (max): 17.5mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: SOT-23-6
• Resolution (bits): 12bit
• Sampling Rate: 1MSPS
• Input Channel Type: Single Ended
• Supply Voltage Range - Analog: 2.7V To 5.25V
• Supply Current: 3.5mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7476ACBZ - BOARD EVALUATION FOR AD7476AAD7476-DBRD - BOARD EVAL FOR AD7476AD7476A-DBRD - BOARD EVAL FOR AD7476A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: AD7476ARTZ-500RL7TR

TIMING SPECIFICATIONS
Parameter
f
t
t
t
t
t
t
t
t
t
t
t
NOTES
1
2
3
4
5
6
7
Specifications subject to change without notice.
REV. D
SCLK
A Version timing specifications apply to the AD7477 S Version and AD7478 S Version; B Version timing specifications apply to the AD7476 S Version.
3 V specifications apply from V
Mark/Space ratio for the SCLK input is 40/60 to 60/40.
Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.0 V.
t
See Power-Up Time section.
CONVERT
QUIET
1
2
3
4
5
6
7
8
POWER-UP
Guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
V
to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
of the part and is independent of the bus loading.
8
5
5
6
DD
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
= 4.75 V to 5.25 V.
4
7
3 V
10
20
12
16 × t
50
10
10
20
40
70
0.4 × t
0.4 × t
10
10
25
1
3
AD7476/AD7477/AD7478
SCLK
SCLK
SCLK
Limit at T
DD
= 2.7 V to 3.6 V for A Version; 3 V specifications apply from V
MIN
5 V
10
20
12
16 × t
50
10
10
20
20
20
0.4 × t
0.4 × t
10
10
25
1
1, 2
, T
Figure 1. Load Circuit for Digital Output Timing
Specifications
3
MAX
(V
SCLK
SCLK
SCLK
DD
= 2.35 V to 5.25 V, T
TO OUTPUT
PIN
Unit
kHz min
MHz max
MHz max
ns min
ns min
ns min
ns max
ns max
ns max
ns min
ns min
ns min
ns min
ns max
µs typ
50pF
C
L
200 A
200 A
–5–
A
= T
MIN
Description
A Version
B Version
Minimum Quiet Time Required between Bus Relinquish and
Start of Next Conversion
Minimum CS Pulsewidth
CS to SCLK Setup Time
Delay from CS until SDATA Three-State Disabled
SCLK Low Pulsewidth
SCLK High Pulsewidth
SCLK to Data Valid Hold Time
SCLK Falling Edge to SDATA High Impedance
Power-Up Time from Full Power-Down
Data Access Time after SCLK Falling Edge, A Version
Data Access Time after SCLK Falling Edge, B Version
SCLK Falling Edge to SDATA High Impedance
to T
I
I
OL
OH
MAX
8
, quoted in the Timing Specifications is the true bus relinquish time
, unless otherwise noted.)
DD
DD
= 2.35 V to 3.6 V for B Version; 5 V specifications apply from
1.6V
) and timed from a voltage level of 1.6 V.
AD7476/AD7477/AD7478