AD7476ARTZ-500RL7 Analog Devices Inc, AD7476ARTZ-500RL7 Datasheet - Page 17

• Manufacturer Part Number: AD7476ARTZ-500RL7
• Description: IC ADC 12BIT 1MSPS SOT-23-6
• Manufacturer: Analog Devices Inc

Specifications of AD7476ARTZ-500RL7

• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Design Resources: Output Channel Monitoring Using AD5380 (CN0008) AD5382 Channel Monitor Function (CN0012) AD5381 Channel Monitor Function (CN0013) AD5383 Channel Monitor Function (CN0015) AD5390/91/92 Channel Monitor Function (CN0030) Power off protected data acquisition signal chain using ADG4612 , AD711, and AD7476 (CN0165)
• Number Of Bits: 12
• Sampling Rate (per Second): 1M
• Number Of Converters: 1
• Power Dissipation (max): 17.5mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: SOT-23-6
• Resolution (bits): 12bit
• Sampling Rate: 1MSPS
• Input Channel Type: Single Ended
• Supply Voltage Range - Analog: 2.7V To 5.25V
• Supply Current: 3.5mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7476ACBZ - BOARD EVALUATION FOR AD7476AAD7476-DBRD - BOARD EVAL FOR AD7476AD7476A-DBRD - BOARD EVAL FOR AD7476A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: AD7476ARTZ-500RL7TR

AD7476/AD7477/AD7478 to DSP56xxx Interface
The connection diagram in Figure 20 shows how the AD7476/
AD7477/AD7478 can be connected to the SSI (Synchronous
Serial Interface) of the DSP56xxx family of DSPs from Motorola.
The SSI is operated in Synchronous Mode (SYN bit in
CRB =1) with internally generated word frame sync for both
Tx and Rx (Bits FSL1 = 0 and FSL0 = 0 in CRB). Set the word
length to 16 by setting bits WL1 = 1 and WL0 = 0 in CRA. To
implement the Power-Down mode on the AD7476/AD7477/
AD7478, the word length can be changed to eight bits by setting
bits WL1 = 0 and WL0 = 0 in CRA. It should be noted that
for signal processing applications, it is imperative that the
frame synchronization signal from the DSP56xxx provides
equidistant sampling.
REV. D
Figure 20. Interfacing to the DSP56xxx
AD7478*
AD7476/
AD7477/
*ADDITIONAL PINS OMITTED FOR CLARITY
SDATA
SCLK
CS
SCK
SRD
SC2
DSP56xxx*
–17–
AD7476/AD7477/AD7478 to MC68HC16 Interface
The Serial Peripheral Interface (SPI) on the MC68HC16 is
configured for Master Mode (MSTR = 1), the Clock Polarity
Bit (CPOL) = 1, and the Clock Phase Bit (CPHA) = 0. The SPI
is configured by writing to the SPI Control Register (SPCR)—see
the 68HC16 User Manual. The serial transfer will take place as
a 16-bit operation when the SIZE bit in the SPCR register is set
to SIZE = 1. To implement the Power-Down mode with an
8-bit transfer, set SIZE = 0. A connection diagram is shown
in Figure 21.
Figure 21. Interfacing to the MC68HC16
AD7478*
AD7476/
AD7477/
*ADDITIONAL PINS OMITTED FOR CLARITY
SDATA
SCLK
AD7476/AD7477/AD7478
CS
SCLK/PMC2
MISO/PMC0
SS/PMC3
MC68HC16*