AD7920BRMZ Analog Devices Inc, AD7920BRMZ Datasheet - Page 17

• Manufacturer Part Number: AD7920BRMZ
• Description: IC ADC 12BIT 250KSPS 8-MSOP
• Manufacturer: Analog Devices Inc

Specifications of AD7920BRMZ

• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Bits: 12
• Sampling Rate (per Second): 250k
• Number Of Converters: 1
• Power Dissipation (max): 15mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-TSSOP, 8-MSOP (0.118", 3.00mm Width)
• Resolution (bits): 12bit
• Sampling Rate: 250kSPS
• Input Channel Type: Differential
• Supply Current: 3mA
• Digital Ic Case Style: SOP
• No. Of Pins: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7920CBZ - BOARD EVALUATION FOR AD7920
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

When power supplies are first applied to the AD7910/AD7920, the
ADC can power up in either power-down mode or in normal
mode. Because of this, it is best to allow a dummy cycle to elapse to
ensure the part is fully powered up before attempting a valid
conversion. Likewise, if the intention is to keep the part in power-
down mode while not in use and the user wishes the part to power
up in power-down mode, the dummy cycle can be used to ensure
the device is in power-down mode by executing a cycle such as that
shown in Figure 20. Once supplies are applied to the
AD7910/AD7920, the power-up time is the same as that when
powering up from power-down mode. It takes approximately 1 μs
to power up fully if the part powers up in normal mode. It is not
necessary to wait 1 μs before executing a dummy cycle to ensure
the desired mode of operation.
SDATA
SCLK
CS
A
1
SDATA
SCLK
SDATA
THE PART
BEGINS TO
POWER UP
SCLK
CS
CS
INVALID DATA
1
10
1
Figure 20. Entering Power-Down Mode
2
Figure 21. Exiting Power-Down Mode
12
Figure 19. Normal Mode Operation
14
Rev. C | Page 17 of 24
16
VALID DATA
10
Instead, the dummy cycle can occur directly after power is
supplied to the ADC. If the first valid conversion is performed
directly after the dummy conversion, care must be taken to
ensure that adequate acquisition time is allowed. As mentioned
earlier, when powering up from the power-down mode, the part
returns to track upon the first SCLK edge applied after the
falling edge of CS . However, when the ADC powers up initially
after supplies are applied, the track-and-hold is in track. This
means, assuming the user has the facility to monitor the ADC
supply current, if the ADC powers up in the desired mode of
operation and thus a dummy cycle is not required to change
mode then a dummy cycle is required to place the track-and-
hold into track.
10
THREE-STATE
12
12
1
14
14
AD7910/AD7920
THE PART IS FULLY
POWERED UP WITH
V
IN
FULLY ACQUIRED
16
16
VALID DATA
AD7910/AD7920
16