AD7920BRMZ Analog Devices Inc, AD7920BRMZ Datasheet - Page 7

• Manufacturer Part Number: AD7920BRMZ
• Description: IC ADC 12BIT 250KSPS 8-MSOP
• Manufacturer: Analog Devices Inc

Specifications of AD7920BRMZ

• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Bits: 12
• Sampling Rate (per Second): 250k
• Number Of Converters: 1
• Power Dissipation (max): 15mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-TSSOP, 8-MSOP (0.118", 3.00mm Width)
• Resolution (bits): 12bit
• Sampling Rate: 250kSPS
• Input Channel Type: Differential
• Supply Current: 3mA
• Digital Ic Case Style: SOP
• No. Of Pins: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7920CBZ - BOARD EVALUATION FOR AD7920
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

TIMING EXAMPLES
Figure 3 and Figure 4 show some of the timing parameters from
Table 3.
TIMING EXAMPLE 1
From Figure 4, having f
250 kSPS gives a cycle time of t
With t
satisfies the requirement of 250 ns for t
comprises 2.5(1/f
allows a value of 954 ns for t
requirement of 50 ns.
2
SDATA
SCLK
= 10 ns min, this leaves t
SCLK
CS
CS
THREE-
STATE
SCLK
t
) + t
2
t
2
Z
SCLK
1
1
t
8
3
ZERO
+ t
= 5 MHz and a throughput rate of
4 LEADING ZEROS
QUIET
QUIET
2
2
+ 12.5(1/f
ACQ
2
, satisfying the minimum
, where t
ZERO
to be 1.49 μs. This 1.49 μs
ACQ
3
3
ZERO
t
. From Figure 4, t
SCLK
8
4
= 36 ns max. This
12.5(1/f
) + t
4
4
Figure 3. AD7920 Serial Interface Timing Diagram
SCLK
DB11
ACQ
t
t
Figure 4. Serial Interface Timing Example
6
CONVERT
)
= 4 μs.
5
t
5
CONVERT
t
DB10
7
ACQ
Rev. C | Page 7 of 24
1/THROUGHPUT
13
13
B
B
DB2
TIMING EXAMPLE 2
The AD7920 can also operate with slower clock frequencies.
From Figure 4, having f
150 kSPS gives a cycle time of t
With t
satisfies the requirement of 250 ns for t
comprises 2.5(1/f
value of 2.19 μs for t
of 50 ns. As in this example and with other slower clock values,
the signal may already be acquired before the conversion is
complete, but it is still necessary to leave 50 ns minimum t
between conversions. In this example, the signal should be fully
acquired at approximately Point C in Figure 4.
14
14
t
5
2
C
DB1
= 10 ns min, this leaves t
15
15
t
8
DB0
SCLK
t
ACQ
QUIET
16
t
) + t
16
8
SCLK
, satisfying the minimum requirement
8
+ t
THREE-STATE
= 3.4 MHz and a throughput rate of
QUIET
2
+ 12.5(1/f
ACQ
t
t
, t
QUIET
QUIET
8
to be 2.97 μs. This 2.97 μs
= 36 ns max. This allows a
t
1
AD7910/AD7920
ACQ
. From Figure 4, t
SCLK
) + t
ACQ
= 6.66 μs.
QUIET
ACQ