AD7920BRMZ Analog Devices Inc, AD7920BRMZ Datasheet - Page 19

• Manufacturer Part Number: AD7920BRMZ
• Description: IC ADC 12BIT 250KSPS 8-MSOP
• Manufacturer: Analog Devices Inc

Specifications of AD7920BRMZ

• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Bits: 12
• Sampling Rate (per Second): 250k
• Number Of Converters: 1
• Power Dissipation (max): 15mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-TSSOP, 8-MSOP (0.118", 3.00mm Width)
• Resolution (bits): 12bit
• Sampling Rate: 250kSPS
• Input Channel Type: Differential
• Supply Current: 3mA
• Digital Ic Case Style: SOP
• No. Of Pins: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7920CBZ - BOARD EVALUATION FOR AD7920
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

SERIAL INTERFACE
Figure 23 and Figure 24 show the detailed timing diagram for
serial interfacing to the AD7920 and AD7910, respectively. The
serial clock provides the conversion clock and also controls the
transfer of information from the AD7910/AD7920 during
conversion.
The CS signal initiates the data transfer and conversion process.
The falling edge of CS puts the track-and-hold into hold mode
and takes the bus out of three-state; the analog input is sampled
at that point. The conversion is also initiated at this point.
For the AD7920, the conversion requires 16 SCLK cycles to
complete. Once 13 SCLK falling edges have elapsed, track-and-
hold goes back into track on the next SCLK rising edge, as
shown in Figure 23 at Point B. On the 16th SCLK falling edge,
the SDATA line goes back into three-state. If the rising edge of
CS occurs before 16 SCLKs have elapsed then the conversion is
terminated and the SDATA line goes back into three-state;
otherwise, SDATA returns to three-state on the 16th SCLK
falling edge, as shown in Figure 23. Sixteen serial clock cycles
are required to perform the conversion process and to access
data from the AD7920.
For the AD7910, the conversion requires 14 SCLK cycles to
complete. Once 13 SCLK falling edges have elapsed, track-and-
hold goes back into track on the next SCLK rising edge, as
shown in Figure 24 at Point B.
SDATA
SDATA
SCLK
SCLK
CS
CS
THREE-
THREE-
STATE
STATE
t
t
2
2
Z
Z
1
t
1
t
3
3
ZERO
ZERO
4 LEADING ZEROS
4 LEADING ZEROS
2
2
ZERO
ZERO
3
3
ZERO
ZERO
t
t
4
4
4
4
Figure 23. AD7920 Serial Interface Timing Diagram
Figure 24. AD7910 Serial Interface Timing Diagram
DB11
DB9
t
t
6
6
5
5
t
t
CONVERT
CONVERT
t
t
DB10
7
7
DB8
Rev. C | Page 19 of 24
1/THROUGHPUT
1/THROUGHPUT
13
13
B
B
DB2
DB0
If the rising edge of CS occurs before 14 SCLKs have elapsed, the
conversion is terminated and the SDATA line goes back into
three-state. If 16 SCLKs are used in the cycle, SDATA returns to
three-state on the 16th SCLK falling edge, as shown in Figure 24.
CS going low clocks out the first leading zero to be read in by
the microcontroller or DSP. The remaining data is then clocked
out by subsequent SCLK falling edges beginning with the
second leading zero. Thus, the first falling clock edge on the
serial clock has the first leading zero provided and also clocks
out the second leading zero. The final bit in the data transfer is
valid on the 16th falling edge, having been clocked out on the
previous (15th) falling edge.
In applications with a slower SCLK, it is possible to read in data on
each SCLK rising edge. In this case, the first falling edge of SCLK
clocks out the second leading zero, which could be read in the first
rising edge. However, the first leading zero that was clocked out
when CS went low is missed unless it was not read in the first
falling edge. The 15th falling edge of SCLK clocks out the last bit
and it could be read in the 15th rising SCLK edge.
If CS goes low just after the SCLK falling edge has elapsed, CS
clocks out the first leading zero as before, and it can be read on the
SCLK rising edge. The next SCLK falling edge clocks out the sec-
ond leading zero and it could be read on the following rising edge.
14
14
t
t
5
5
2 TRAILING ZEROS
ZERO
DB1
15
15
ZERO
DB0
t
t
16
8
16
8
THREE-STATE
THREE-STATE
t
t
QUIET
QUIET
t
t
1
1
AD7910/AD7920