AD7328BRUZ Analog Devices Inc, AD7328BRUZ Datasheet - Page 31

• Manufacturer Part Number: AD7328BRUZ
• Description: IC ADC 12BIT+ SAR 8CHAN 20TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD7328BRUZ

• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Design Resources: Using AD7328 in Appls with Single-Ended Industrial-Level Signals (CN0047)
• Number Of Bits: 12
• Sampling Rate (per Second): 1M
• Number Of Converters: 1
• Power Dissipation (max): 30mW
• Voltage Supply Source: Dual ±
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP (0.173", 4.40mm Width)
• Resolution (bits): 13bit
• Sampling Rate: 1MSPS
• Input Channel Type: Pseudo Differential, Single Ended
• Supply Current: 900µA
• Digital Ic Case Style: TSSOP
• No. Of Pins: 20
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7328CBZ - BOARD EVALUATION FOR AD7328
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

SERIAL INTERFACE
Figure 53 shows the timing diagram for the serial interface of
the AD7328. The serial clock applied to the SCLK pin provides
the conversion clock and controls the transfer of information to
and from the AD7328 during a conversion.
The
process. The falling edge of CS
hold mode and takes the bus out of three-state. The analog
input signal is then sampled. Once the conversion is initiated,
it requires 16 SCLK cycles to complete.
The track-and-hold goes back into track mode on the 14
rising edge. On the 16
to three-state. If the rising edge of
have elapsed, the conversion is terminated and the DOUT line
returns to three-state. Depending on where the CS signal is brought
high, the addressed register may be updated.
Data is clocked into the AD7328 on the SCLK falling edge. The
three MSBs on the DIN line are decoded to select which register
is addressed. The control register is a 12-bit register. If the control
register is addressed by the three MSBs, the data on the DIN line
is loaded into the control on the 15
quence register or either of the range registers is addressed, the
data on the DIN line is loaded into the addressed register on the
11
th
SCLK falling edge.
CS
signal initiates the data transfer and the conversion
DOUT
SCLK
DIN
CS
THREE-
STATE
th
SCLK falling edge, the DOUT line returns
WRITE
ADD2
t
2
1
3 IDENTIFICATION BITS
ADD1
puts the track-and-hold into
t
3
CS occurs before 16 SCLK cycles
t
SEL1
9
REG
th
2
SCLK rising edge. If the se-
ADD0
SEL2
REG
Figure 53. Serial Interface Timing Diagram (Control Register Write)
3
SIGN
MSB
4
DB11
t
t
6
4
t
CONVERT
th
t
10
5
SCLK
t
DB10
7
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Conversion data is clocked out of the AD7328 on each SCLK
falling edge. Data on the DOUT line consists of three channel
identifier bits, a sign bit, and a 12-bit conversion result. The
channel identifier bits are used to indicate which channel
corresponds to the conversion result.
If the Weak/
than returning to true three-state upon the 16
edge, the DOUT line is pulled weakly to the logic level corres-
ponding to ADD3 of the next serial transfer. This is done to
ensure that the MSB of the next serial transfer is set up in time
for the first SCLK falling edge after the
Weak/
true three-state between conversions, then depending on the
particular processor interfacing to the AD7328, the ADD3 bit
may be valid in time for the processor to clock it in successfully.
If the Weak/
line has been driven to ADD3 since the previous conversion, it
is nevertheless so weakly driven that another device could take
control of the bus. This will not lead to a bus contention issue
because, for example, a 10 kΩ pull-up or pull-down resistor is
sufficient to overdrive the logic level of ADD3. When the Weak/
Three-State bit is set to 1, the ADD3 is typically valid 9 ns after
the CS falling edge, compared with 14 ns when the DOUT line
returns to three-state at the end of the conversion.
DB2
14
t
5
Three-State bit is set to 0 and the DOUT line returns to
DB1
LSB
Three-State
Three-State bit is set to 1, then although the DOUT
15
DB0
DON’T
CARE
16
THREE-STATE
t
8
bit is set in the control register, rather
t
QUIET
t
1
CS falling edge. If the
th
SCLK falling
AD7328