ADC10D020CIVS/NOPB National Semiconductor, ADC10D020CIVS/NOPB Datasheet
ADC10D020CIVS/NOPB
Specifications of ADC10D020CIVS/NOPB
*ADC10D020CIVS/NOPB
ADC10D020CIVS
Available stocks
Related parts for ADC10D020CIVS/NOPB
ADC10D020CIVS/NOPB Summary of contents
Page 1
... Operating over the industrial (−40° ture range, the ADC10D020 is available in a 48-pin TQFP. An evaluation board is available to ease the design effort. Ordering Information Device ADC10D020CIVS ADC10D020CIVSE ADC10D020CIVSX ADC10D020EVAL © 2010 National Semiconductor Corporation ADC10D020 Features ■ Internal sample-and-hold ■ Internal reference capability ■ Dual gain settings ■ ...
Page 2
Connection Diagram Block Diagram www.national.com 20025501 TOP VIEW 2 20025502 ...
Page 3
Pin Descriptions and Equivalent Circuits Pin No. Symbol Equivalent Circuit I− Q− REF V 45 CMO Description Analog inputs to “I” ADC. Nominal conversion range is ...
Page 4
Pin No. Symbol 33 CLK STBY GAIN 8 thru 27 I0–I9 and Q0–Q9 28 I www.national.com Equivalent Circuit Digital ...
Page 5
Pin No. Symbol 3, 39, 42, 46 AGND 5 DGND GND Equivalent Circuit The ground return for the analog supply. AGND and DGND should be connected together close to the ADC10D020 package. The ground return for the ...
Page 6
... Absolute Maximum Ratings (Note 1, Note 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Positive Supply Voltages Voltage on Any Pin Input Current at Any Pin (Note 3) Package Input Current (Note 3) Package Dissipation 25°C ...
Page 7
Symbol Parameter HS2 Second Harmonic HS3 Third Harmonic SFDR Spurious Free Dynamic Range IMD Intermodulation Distortion Overrange Output Code Underrange Output Code FPBW Full Power Bandwidth INTER-CHANNEL CHARACTERISTICS Crosstalk Channel - Channel Aperture Delay Match Channel - Channel Gain Matching ...
Page 8
Symbol Parameter POWER SUPPLY CHARACTERISTICS Core Supply Current A D Digital Output Driver Supply Current I DR (Note 10) PWR Power Consumption PSRR1 Power Supply Rejection Ratio PSRR2 Power Supply Rejection Ratio AC Electrical Characteristics OS = ...
Page 9
AC Electrical Characteristics OS = High (Parallel Mode) The following specifications apply for V V (a.c. coupled) = FSR = 1 P-P Boldface limits apply for MIN Symbol Parameter f Maximum Clock ...
Page 10
Note 9: Test limits are guaranteed to National's AOQL (Average Outgoing Quality Level). Performance is guaranteed only 50%. The limits for V and clock duty cycle specify the range over which reasonable performance is expected. Tests are ...
Page 11
ADC10D020 Timing Diagram for Parallel Mode 20025509 FIGURE 1. AC Test Circuit 11 20025507 www.national.com ...
Page 12
Specification Definitions APERTURE (SAMPLING) DELAY is that time required after the fall of the clock input for the sampling switch to open. The Sample/Hold circuit effectively stops capturing the input sig- nal and goes into the “hold” mode t AD ...
Page 13
Typical Performance Characteristics Typical INL INL vs. V REF 3.0V MHz, unless otherwise specified CLK INL vs. Supply Voltage 20025511 INL vs. f 20025513 13 20025512 CLK 20025514 ...
Page 14
INL vs. Clock Duty Cycle Typical DNL DNL vs. V www.national.com 20025515 20025517 REF 20025519 14 INL vs. Temperature 20025516 DNL vs. Supply Voltage 20025518 DNL vs. f CLK 20025520 ...
Page 15
DNL vs. Clock Duty Cycle 20025521 SNR vs. Supply Voltage @ MHz to 9.5 MHz IN 20025523 SNR vs 9.5 MHz CLK IN 20025525 DNL vs. Temperature SNR vs. V REF @ f ...
Page 16
SNR vs. Clock Duty Cycle @ f = 4.7 MHz IN SNR vs SINAD & ENOB vs. Supply Voltage @ f to 9.5 MHz www.national.com 20025527 = 9.5 MHz SNR vs. Temperature @ f 20025529 ...
Page 17
SINAD & ENOB vs 9.5 MHz) CLK IN SINAD & ENOB vs. Clock Duty Cycle @ f SINAD & ENOB vs 9.5 MHz CM IN SINAD & ENOB vs. f 20025533 = ...
Page 18
Distortion vs. Supply Voltage @ f Distortion vs CLK Distortion vs. Clock Duty Cycle @ f www.national.com = 4.7 MHz IN 20025539 = 9.5 MHz IN 20025541 = 4.7 MHz IN 20025543 18 Distortion vs ...
Page 19
Distortion vs 4.7 MHz CM IN SFDR vs. Supply Voltage @ f = 4.7 MHz IN SFDR vs 9.5 MHz CLK IN Distortion vs. Temperature 20025545 SFDR vs. V 20025547 SFDR vs. ...
Page 20
SFDR vs. Clock Duty Cycle @ f SFDR vs Crosstalk vs. f www.national.com = 4.7 MHz IN 20025551 = 4.7 MHz SFDR vs. Temperature @ f 20025553 IN 20025555 20 SFDR vs ...
Page 21
Crosstalk vs 4.7 MHz CM IN Power Consumption vs. Temperature Spectral Response @ f = 4.7 MHz IN Crosstalk vs. Temperature 20025557 Spectral Response @ f 20025561 Spectral Response @ f 20025563 21 20025558 = 1 ...
Page 22
Spectral Response @ f Spectral Response @ f Functional Description Using a subranging architecture, the ADC10D020 achieves 9.5 effective bits over the entire Nyquist band at 20 MSPS while consuming just 150 mW. The use of an internal sample- and-hold ...
Page 23
Applications Information 1.0 THE ANALOG SIGNAL INPUTS Each of the analog inputs of the ADC10D020 consists of a switch (transmission gate) followed by a switched capacitor amplifier. The capacitance seen at each input pin changes with the clock level, appearing ...
Page 24
FIGURE 4. Simple Reference Biasing 24 20025571 ...
Page 25
FIGURE 5. Improved Low Component Count Reference Biasing The V output can be used as the ADC reference source CMO as long as care is taken to prevent excessive loading of this pin. However, the V output was not designed ...
Page 26
FIGURE 6. Setting An Accurate Reference Voltage 26 20025573 ...
Page 27
FIGURE 7. The V output pin may be used as an internal reference source if its output is divided down and not loaded CMO 2.1 REFERENCE VOLTAGE The reference voltage should be within the range specified in the Operating Ratings ...
Page 28
ADC clock pin should be AC terminated, near the clock input, with a series RC to ground. The resistor value should equal the characteristic impedance, Z line and the capacitor should have a value such that C ...
Page 29
POWER SUPPLY CONSIDERATIONS A/D converters draw sufficient transient current to corrupt their own power supplies if not adequately bypassed µ µF tantalum or aluminum electrolytic capacitor should be placed within half an inch (1.2 centimeters) ...
Page 30
DYNAMIC PERFORMANCE The ADC10D020 is a.c. tested and its dynamic performance is guaranteed. To meet the published specifications, the clock source driving the CLK input must be free of jitter. For best dynamic performance, isolating the ADC clock from ...
Page 31
Physical Dimensions inches (millimeters) unless otherwise noted NOTES UNLESS OTHERWISE SPECIFIED 1. STANDARD LEAD FINISH 7.62 MICROMETERS MINIMUM SOLDER PLATING (85/15) THICKNESS ON ALLOY 42/COPPER. 2. DIMENSION DOES NOT INCLUDE MOLD PROTRUSION. MAXIMUM ALLOWABLE MOLD PROTRUSION 0.15 mm PER SIDE. ...
Page 32
... For more National Semiconductor product information and proven design tools, visit the following Web sites at: www.national.com Products Amplifiers www.national.com/amplifiers Audio www.national.com/audio Clock and Timing www.national.com/timing Data Converters www.national.com/adc Interface www.national.com/interface LVDS www.national.com/lvds Power Management www.national.com/power Switching Regulators www.national.com/switchers LDOs www.national.com/ldo LED Lighting www ...