ADC10D020CIVS/NOPB National Semiconductor, ADC10D020CIVS/NOPB Datasheet - Page 12

• Manufacturer Part Number: ADC10D020CIVS/NOPB
• Description: IC ADC 10BIT 48-TQFP
• Manufacturer: National Semiconductor

Specifications of ADC10D020CIVS/NOPB

• Number Of Bits: 10
• Sampling Rate (per Second): 20M
• Number Of Converters: 2
• Power Dissipation (max): 150mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-VFQFP
• Number Of Elements: 2
• Resolution: 10Bit
• Architecture: Pipelined
• Sample Rate: 20MSPS
• Input Polarity: Bipolar
• Input Type: Voltage
• Rated Input Volt: ±0.5/±1V
• Differential Input: Yes
• Power Supply Requirement: Analog and Digital
• Single Supply Voltage (typ): 3V
• Single Supply Voltage (min): 2.7V
• Single Supply Voltage (max): 3.6V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Differential Linearity Error: -1LSB/1.2LSB
• Integral Nonlinearity Error: ±1.8LSB
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: TQFP
• Input Signal Type: Differential
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *ADC10D020CIVS; *ADC10D020CIVS/NOPB; ADC10D020CIVS

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Specification Definitions
APERTURE (SAMPLING) DELAY is that time required after
the fall of the clock input for the sampling switch to open. The
Sample/Hold circuit effectively stops capturing the input sig-
nal and goes into the “hold” mode t
APERTURE JITTER is the variation in aperture delay from
sample to sample. Aperture jitter shows up as input noise.
CLOCK DUTY CYCLE is the ratio of the time that the clock
waveform is high to the total time of one clock period.
CROSSTALK is coupling of energy from one channel into the
other channel.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of
the maximum deviation from the ideal step size of 1 LSB.
Measured at 20 MSPS with a ramp input.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE
BITS) is another method of specifying Signal-to-Noise and
Distortion Ratio, or SINAD. ENOB is defined as (SINAD −
1.76)/6.02 and says that the converter is equivalent to a per-
fect ADC of this (ENOB) number of bits.
FULL POWER BANDWIDTH (FPBW) is the frequency at
which the magnitude of the reconstructed output fundamental
drops 3 dB below its 1 MHz value.
GAIN ERROR is the difference between the ideal and actual
differences between the input levels at which the first and last
code transitions occur. That is, how far this difference is from
Full Scale.
INTEGRAL NON LINEARITY (INL) is a measure of the max-
imum deviation of each individual code from a line drawn from
zero scale (½ LSB below the first code transition) through
positive full scale (½ LSB above the last code transition). The
deviation of any given code from this straight line is measured
from the center of that code value. The end point test method
is used. Measured at 20 MSPS with a ramp input.
INTERMODULATION DISTORTION (IMD) is the creation of
spectral components that are not present in the input as a
result of two sinusoidal frequencies being applied to the ADC
input at the same time. It is defined as the ratio of the power
in the second and third order intermodulation products to the
total power in one of the original frequencies. IMD is usually
expressed in dB.
LSB (LEAST SIGNIFICANT BIT) is the bit that has the small-
est value of weight of all bits. This value is
where “m” is the reference scale factor and “n” is the ADC
resolution, which is 10 in the case of the ADC10D020. The
value of “m” is determined by the logic level at the gain pin
and has a value of 1 when the gain pin is at a logic low and a
value of 2 when the gain pin is at a logic high.
MISSING CODES are those output codes that are skipped or
will never appear at the ADC outputs. These codes cannot be
reached with any input value.
m * V
REF
/2
AD
n
after the clock goes low.
12
MSB (MOST SIGNIFICANT BIT) is the bit that has the largest
value or weight. Its value is one half of full scale.
OFFSET ERROR is a measure of how far the mid-scale tran-
sition point is from the ideal zero voltage input.
OUTPUT DELAY is the time delay after the rising edge of the
input clock before the data update is present at the output
pins.
OVERRANGE RECOVERY TIME is the time required after
the differential input voltages goes from 1.5V to 0V for the
converter to recover and make a conversion with its rated ac-
curacy.
PIPELINE DELAY (LATENCY) is the number of clock cycles
between initiation of conversion and when that data is pre-
sented to the output driver stage. New data is available at
every clock cycle, but the data output lags the input by the
Pipeline Delay plus the Output Delay.
POWER SUPPLY REJECTION RATIO (PSRR) can be one
of two specifications. PSRR1 (DC PSRR) is the ratio of the
change in full scale gain error that results from a power supply
voltage change from 2.7V to 3.6V. PSRR2 (AC PSRR) is
measured with a 20 MHz, 250 mV
power supply and is the ratio of the signal amplitude on the
power supply pins to the amplitude of that frequency at the
output. PSRR is expressed in dB.
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in
dB, of the rms value of the fundamental signal at the output
to the rms value of the sum of all other spectral components
below one-half the sampling frequency, not including har-
monics or dc.
SIGNAL TO NOISE PLUS DISTORTION (S/(N+D) or
SINAD) is the ratio, expressed in dB, of the rms value of the
fundamental signal at the output to the rms value of all of the
other spectral components below half the clock frequency,
including harmonics but excluding dc.
SPURIOUS FREE DYNAMIC RANGE (SFDR) is the differ-
ence, expressed in dB, between the rms values of the funda-
mental signal at the output and the peak spurious signal,
where a spurious signal is any signal present in the output
spectrum that is not present at the input.
TOTAL HARMONIC DISTORTION (THD) is the ratio, ex-
pressed in dB, of the rms total of the first 9 harmonic levels to
the level of the input frequency. THD is calculated as
where f
quency and f
harmonic frequencies in the output spectrum.
1
is the RMS power of the fundamental (output) fre-
2
through f
10
are the RMS power of the first 9
P-P
signal riding upon the