ADC10D020CIVS/NOPB National Semiconductor, ADC10D020CIVS/NOPB Datasheet - Page 4

• Manufacturer Part Number: ADC10D020CIVS/NOPB
• Description: IC ADC 10BIT 48-TQFP
• Manufacturer: National Semiconductor

Specifications of ADC10D020CIVS/NOPB

• Number Of Bits: 10
• Sampling Rate (per Second): 20M
• Number Of Converters: 2
• Power Dissipation (max): 150mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-VFQFP
• Number Of Elements: 2
• Resolution: 10Bit
• Architecture: Pipelined
• Sample Rate: 20MSPS
• Input Polarity: Bipolar
• Input Type: Voltage
• Rated Input Volt: ±0.5/±1V
• Differential Input: Yes
• Power Supply Requirement: Analog and Digital
• Single Supply Voltage (typ): 3V
• Single Supply Voltage (min): 2.7V
• Single Supply Voltage (max): 3.6V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Differential Linearity Error: -1LSB/1.2LSB
• Integral Nonlinearity Error: ±1.8LSB
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: TQFP
• Input Signal Type: Differential
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *ADC10D020CIVS; *ADC10D020CIVS/NOPB; ADC10D020CIVS

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8 thru 27
Pin No.
40, 41
6, 30
33
31
32
34
35
36
28
2
4
I0–I9 and Q0–Q9
Symbol
STBY
GAIN
CLK
V
OS
OC
OF
PD
I/Q
V
V
DR
A
D
Equivalent Circuit
4
Digital clock input for both converters. The analog inputs are
sampled on the falling edge of this clock input.
Output Bus Select. With this pin at a logic high, both the “I” and the
“Q” data are present on their respective 10-bit output buses
(Parallel mode of operation). When this pin is at a logic low, the “I”
and “Q” data are multiplexed onto the “I” output bus and the “Q”
output lines all remain at a logic low (multiplexed mode).
Offset Correct pin. A low-to-high transition on this pin initiates an
independent offset correction sequence for each converter, which
takes 34 clock cycles to complete. During this time 32 conversions
are taken and averaged. The result is subtracted from subsequent
conversions. Each input pair should have 0V differential value
during this entire 34 clock period.
Output Format pin. When this pin is LOW the output format is Offset
Binary. When this pin is HIGH the output format is 2's complement.
This pin may be changed asynchronously, but this will result in
errors for one or two conversions.
Standby pin. The device operates normally with a logic low on this
and the PD (Power Down) pin. With this pin at a logic high and the
PD pin at a logic low, the device is in the standby mode where it
consumes just 27 mW of power. It takes just 800 ns to come out of
this mode after the STBY pin is brought low.
Power Down pin that, when high, puts the converter into the Power
Down mode where it consumes less than 1 mW of power. It takes
less than 1 ms to recover from this mode after the PD pin is brought
low. If both the STBY and PD pins are high simultaneously, the PD
pin dominates.
This pin sets the internal signal gain at the inputs to the ADCs. With
this pin low the full scale differential input peak-to-peak signal is
equal to V
to-peak signal is equal to 2 x V
3V TTL/CMOS-compatible Digital Output pins that provide the
conversion results of the I and Q inputs. I0 and Q0 are the LSBs,
I9 and Q9 are the MSBs. Valid data is present just after the rising
edge of the CLK input in the Parallel mode. In the multiplexed
mode, I-channel data is valid on I0 through I9 when the I/Q output
is high and the Q-channel data is valid on I0 through I9 when the
I/Q output is low.
Output data valid signal. In the multiplexed mode, this pin
transitions from low to high when the data bus transitions from Q-
data to I-data, and from high to low when the data bus transitions
from I-data to Q-data. In the Parallel mode, this pin transitions from
low to high as the output data changes.
Positive analog supply pin. This pin should be connected to a quiet
voltage source of +2.7V to +3.6V. V
common supply and be separately bypassed with 10 µF to 50 µF
capacitors in parallel with 0.1 µF capacitors.
Digital supply pin. This pin should be connected to a quiet voltage
source of +2.7V to +3.6V. V
and be separately bypassed with 10 µF to 50 µF capacitors in
parallel with 0.1 µF capacitors.
Digital output driver supply pins. These pins should be connected
to a voltage source of +1.5V to V
50 µF capacitors in parallel with 0.1 µF capacitors.
REF
. With this pin high the full scale differential input peak-
Description
A
and V
REF
D
..
D
and be bypassed with 10 µF to
A
should have a common supply
and V
D
should have a