LTC1273BCSW Linear Technology, LTC1273BCSW Datasheet - Page 17

• Manufacturer Part Number: LTC1273BCSW
• Description: IC A/D CONV 12BIT SAMPLNG 24SOIC
• Manufacturer: Linear Technology

Specifications of LTC1273BCSW

• Number Of Bits: 12
• Sampling Rate (per Second): 300k
• Data Interface: Parallel
• Number Of Converters: 1
• Power Dissipation (max): 75mW
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (0.300", 7.50mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: LTC1273BCS

A
that the 4MSBs appear on data output D11...D8 during
both READ operations.
ROM Mode, Parallel Read (HBEN = LOW)
The ROM Mode avoids placing a microprocessor into a
WAIT state. A conversion is started with a READ opera-
tion, and the 12 bits of data from the previous conversion
are available on data outputs D11...D0/8 (see Figure 15
and Table 4). This data may be disregarded if not re-
quired. A second READ operation reads the new data
(DB11...DB0) and starts another conversion. A delay at
least as long as the ADC’s conversion time plus the 600ns
minimum delay between conversions must be allowed
between READ operations.
ROM Mode, Two Byte Read
As previously mentioned for a two byte read, only data
outputs D7...D0/8 are used. Conversion is started in the
PPLICATI
TRACK
HBEN
BUSY
HOLD
DATA
RD
RD
CS
O
Table 3. Slow Memory Mode, Two Byte Read Data Bus Status
Data Outputs
First Read
Second Read
U
S
t
8
t
1
t
I FOR ATIO
t
12
t
3
2
U
DB7
Low
Figure 14. Slow Memory Mode, Two Byte Read Timing Diagram
D7
OLD DATA
DB7-DB0
t
CONV
W
DB6
Low
D6
t
6
U
DB5
Low
D5
NEW DATA
DB7-DB0
t
5
t
t
DB4
Low
7
9
D4
normal way with a READ operation and the data output
status is the same as the ROM mode, Parallel Read (see
Figure 16 timing diagram and Table 5 data bus status).
Two more READ operations are required to access the new
conversion result. A delay equal at the ADCs’ conversion
time must be allowed between conversion start and the
third data READ operation. The second READ operation
with HBEN high disables conversion start and places the
high byte (4MSBs) on data outputs D3/11...D0/8. A third
read operation accesses the low data byte (DB7...DB0)
and starts another conversion. The 4MSBs appear on data
outputs D11...D8 during all three read operations.
MICROPROCESSOR INTERFACING
The LTC1273/LTC1275/LTC1276 allow easy interfac-
ing to digital signal processors as well as modern high
speed, 8-bit or 16-bit microprocessors. Here are sev-
eral examples.
t
10
D3/11
DB11
DB3
t
8
t
11
t
1
D2/10
DB10
DB2
t
3
NEW DATA
t
DB11-DB8
4
LTC1275/LTC1276
D1/9
DB1
DB9
t
t
5
7
t
9
t
10
D0/8
DB0
DB8
LTC1273/75/76 • F14
t
12
LTC1273
17
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