AD9258BCPZ-125 Analog Devices Inc, AD9258BCPZ-125 Datasheet - Page 33

• Manufacturer Part Number: AD9258BCPZ-125
• Description: IC ADC 14BIT 125MSPS DL 64LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD9258BCPZ-125

• Data Interface: Serial
• Design Resources: High Performance, Dual Channel IF Sampling Receiver (CN0140)
• Number Of Bits: 14
• Sampling Rate (per Second): 125M
• Number Of Converters: 2
• Power Dissipation (max): 788mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Resolution (bits): 14bit
• Sampling Rate: 125MSPS
• Input Channel Type: Differential
• Supply Voltage Range - Analog: 1.7V To 1.9V
• Supply Voltage Range - Digital: 1.7V To 1.9V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

As detailed in the
Speed ADCs via SPI, the data format can be selected for offset
binary, twos complement, or gray code when using the SPI control.
Table 12. SCLK/DFS Mode Selection (External Pin Mode)
Voltage at Pin
AGND
AVDD
Digital Output Enable Function (OEB)
The AD9258 has a flexible three-state ability for the digital output
pins. The three-state mode is enabled using the OEB pin or
through the SPI. If the OEB pin is low, the output data drivers and
DCOs are enabled. If the OEB pin is high, the output data drivers
and DCOs are placed in a high impedance state. This OEB
function is not intended for rapid access to the data bus. Note
that OEB is referenced to the digital output driver supply
(DRVDD) and should not exceed that supply voltage.
When using the SPI, the data outputs and DCO of each channel
can be independently three-stated by using the output enable
bar bit (Bit 4) in Register 0x14.
Table 13. Output Data Format
Input (V)
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
AN-877
SCLK/DFS
Offset binary
(default)
Twos complement
Condition (V)
< −VREF − 0.5 LSB
= −VREF
= 0
= +VREF − 1.0 LSB
> +VREF − 0.5 LSB
Application Note, Interfacing to High
SDIO/DCS
DCS disabled
DCS enabled
(default)
Offset Binary Output Mode
00 0000 0000 0000
00 0000 0000 0000
10 0000 0000 0000
11 1111 1111 1111
11 1111 1111 1111
Rev. A | Page 33 of 44
TIMING
The AD9258 provides latched data with a pipeline delay of
12 clock cycles. Data outputs are available one propagation
delay (t
The length of the output data lines and loads placed on them
should be minimized to reduce transients within the AD9258.
These transients can degrade converter dynamic performance.
The lowest typical conversion rate of the AD9258 is 10 MSPS.
At clock rates below 10 MSPS, dynamic performance can degrade.
Data Clock Output (DCO)
The AD9258 provides two data clock output (DCO) signals
intended for capturing the data in an external register. In CMOS
output mode, the data outputs are valid on the rising edge of DCO,
unless the DCO clock polarity has been changed via the SPI. In
LVDS output mode, the DCO and data output switching edges
are closely aligned. Additional delay can be added to the DCO
output using SPI Register 0x17 to increase the data setup time.
In this case, the Channel A output data is valid on the rising
edge of DCO, and the Channel B output data is valid on the
falling edge of DCO. See Figure 2, Figure 3, and Figure 4 for
a graphical timing description of the output modes.
PD
) after the rising edge of the clock signal.
Twos Complement Mode
10 0000 0000 0000
10 0000 0000 0000
00 0000 0000 0000
01 1111 1111 1111
01 1111 1111 1111
AD9258
OR
1
0
0
0
1