AD9258BCPZ-125 Analog Devices Inc, AD9258BCPZ-125 Datasheet - Page 35

• Manufacturer Part Number: AD9258BCPZ-125
• Description: IC ADC 14BIT 125MSPS DL 64LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD9258BCPZ-125

• Data Interface: Serial
• Design Resources: High Performance, Dual Channel IF Sampling Receiver (CN0140)
• Number Of Bits: 14
• Sampling Rate (per Second): 125M
• Number Of Converters: 2
• Power Dissipation (max): 788mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Resolution (bits): 14bit
• Sampling Rate: 125MSPS
• Input Channel Type: Differential
• Supply Voltage Range - Analog: 1.7V To 1.9V
• Supply Voltage Range - Digital: 1.7V To 1.9V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SERIAL PORT INTERFACE (SPI)
The AD9258 serial port interface (SPI) allows the user to
configure the converter for specific functions or operations
through a structured register space provided inside the ADC.
The SPI gives the user added flexibility and customization,
depending on the application. Addresses are accessed via the
serial port and can be written to or read from via the port.
Memory is organized into bytes that can be further divided into
fields, which are documented in the Memory Map section. For
detailed operational information, see the AN-877 Application
Note, Interfacing to High Speed ADCs via SPI.
CONFIGURATION USING THE SPI
Three pins define the SPI of this ADC: the SCLK/DFS pin, the
SDIO/DCS pin, and the CSB pin (see Table 14). The SCLK/DFS
(a serial clock) is used to synchronize the read and write data
presented from and to the ADC. The SDIO/DCS (serial data
input/output) is a dual-purpose pin that allows data to be sent
to and read from the internal ADC memory map registers. The
CSB (chip select bar) is an active-low control that enables or
disables the read and write cycles.
Table 14. Serial Port Interface Pins
Pin
SCLK
SDIO
CSB
SCLK
SDIO
CSB
DON’T CARE
DON’T CARE
Function
Serial Clock. The serial shift clock input, which is used to
synchronize serial interface reads and writes.
Serial Data Input/Output. A dual-purpose pin that
typically serves as an input or an output, depending on
the instruction being sent and the relative position in the
timing frame.
Chip Select Bar. An active-low control that gates the read
and write cycles.
t
S
R/W
t
DS
W1
W0
t
DH
A12
t
HIGH
A11
Figure 84. Serial Port Interface Timing Diagram
t
LOW
A10
A9
Rev. A | Page 35 of 44
t
CLK
A8
A7
The falling edge of the CSB, in conjunction with the rising edge
of the SCLK, determines the start of the framing. An example of
the serial timing and its definitions can be found in Figure 84
and Table 5.
Other modes involving the CSB are available. When the CSB is
held low indefinitely, which permanently enables the device,
this is called streaming. The CSB can stall high between bytes to
allow for additional external timing. When CSB is tied high, SPI
functions are placed in high impedance mode. This mode turns
on any SPI pin secondary functions.
During an instruction phase, a 16-bit instruction is transmitted.
Data follows the instruction phase, and its length is determined
by the W0 and W1 bits.
In addition to word length, the instruction phase determines
whether the serial frame is a read or write operation, allowing
the serial port to be used both to program the chip and to read
the contents of the on-chip memory. The first bit of the first byte in
a multibyte serial data transfer frame indicates whether a read
command or a write command is issued. If the instruction is a
readback operation, performing a readback causes the serial
data input/output (SDIO) pin to change direction from an input to
an output at the appropriate point in the serial frame.
All data is composed of 8-bit words. Data can be sent in MSB-
first mode or in LSB-first mode. MSB first is the default on
power-up and can be changed via the SPI port configuration
register. For more information about this and other features,
see the AN-877 Application Note, Interfacing to High Speed
ADCs via SPI.
D5
D4
D3
D2
D1
D0
t
H
DON’T CARE
AD9258
DON’T CARE