AD9258BCPZ-125 Analog Devices Inc, AD9258BCPZ-125 Datasheet - Page 39

• Manufacturer Part Number: AD9258BCPZ-125
• Description: IC ADC 14BIT 125MSPS DL 64LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD9258BCPZ-125

• Data Interface: Serial
• Design Resources: High Performance, Dual Channel IF Sampling Receiver (CN0140)
• Number Of Bits: 14
• Sampling Rate (per Second): 125M
• Number Of Converters: 2
• Power Dissipation (max): 788mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Resolution (bits): 14bit
• Sampling Rate: 125MSPS
• Input Channel Type: Differential
• Supply Voltage Range - Analog: 1.7V To 1.9V
• Supply Voltage Range - Digital: 1.7V To 1.9V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Address
(Hex)
0x0E
0x0F
0x10
0x14
0x16
0x17
0x18
0x24
0x25
0x30
Digital Feature Control
0x100
Register
Name
BIST enable
(global)
ADC input
(global)
Offset adjust
(local)
Output mode
Clock phase
control
(global)
DCO output
delay (global)
VREF select
(global)
BIST signature
LSB (local)
BIST signature
MSB (local)
Dither enable
(local)
Sync control
(global)
Bit 7
(MSB)
Open
Open
Drive
strength
0 = ANSI
LVDS;
1 =
reduced
swing
LVDS
(global)
Invert
DCO clock
Open
Open
Open
01 = 1.5 V p-p
10 = 1.75 V p-p
11 = 2.0 V p-p (default)
00 = 1.25 V p-p
Reference voltage
selection
Open
Open
Open
Bit 6
Output
type
0 = CMOS
1 = LVDS
(global)
Open
Open
Open
Open
Open
Open
Open
Bit 5
CMOS
output
Interleave
enable
(global)
Open
Open
Open
Offset adjust in LSBs from +127 to −128
(twos complement format)
Dither
Enable
Bit 4
Open
Open
Output
enable
bar
(local)
Open
Open
Open
Rev. A | Page 39 of 44
BIST signature[15:8]
BIST signature[7:0]
Bit 3
Open
Open
Open
(must be
written
low)
(global)
Open
Open
Open
Open
(delay = 2500 ps × register value/31)
DCO clock delay
00000 = 0 ps
00001 = 81 ps
00010 = 161 ps
…
11110 = 2419 ps
11111 = 2500 ps
Bit 2
Reset BIST
sequence
Open
Output
invert
(local)
Open
Clock
divider
next sync
only
Open
Input clock divider phase adjust
000 = no delay
001 = 1 input clock cycle
010 = 2 input clock cycles
011 = 3 input clock cycles
100 = 4 input clock cycles
101 = 5 input clock cycles
110 = 6 input clock cycles
111 = 7 input clock cycles
Open
Bit 1
Open
Open
Open
Clock
divider
sync
enable
Output format
00 = offset binary
01 = twos complement
01 = gray code
11 = offset binary
(local)
Bit 0
(LSB)
BIST
enable
Common-
mode
servo
enable
Open
Master
sync
enable
Open
0x00
0x00
0x00
0x00
Default
Value
(Hex)
0x04
0x00
0x00
0x00
0x00
0xC0
0x00
AD9258
Default
Notes/
Comments
Configures the
outputs and
the format of
the data
Allows
selection of
clock delays
into the input
clock divider
Read only
Read only