LTC2208CUP-14 Linear Technology, LTC2208CUP-14 Datasheet - Page 15

• Manufacturer Part Number: LTC2208CUP-14
• Description: IC ADC 14BIT 130MSPS 64-QFN
• Manufacturer: Linear Technology

Specifications of LTC2208CUP-14

• Number Of Bits: 14
• Sampling Rate (per Second): 130M
• Data Interface: Parallel
• Number Of Converters: 1
• Power Dissipation (max): 1.78W
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-WFQFN, Exposed Pad
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

PIN FUNCTIONS
PGA (Pin 64): Programmable Gain Amplifi er Control Pin.
Low selects a front-end gain of 1, input range of 2.25V
High selects a front-end gain of 1.5, input range of
1.5V
GND (Exposed Pad): ADC Power Ground. The exposed
pad on the bottom of the package must be soldered to
ground.
For LVDS Mode. Standard or Low Power
SENSE (Pin 1): Reference Mode Select and External
Reference Input. Tie SENSE to V
2.5V bandgap reference. An external reference of 2.5V or
1.25V may be used; both reference values will set a full
scale ADC range of 2.25V (PGA = 0).
GND (Pins 2, 4, 7, 10, 11, 14, 18): ADC Power Ground.
V
mon mode. Must be bypassed to ground with a minimum
of 2.2μF . Ceramic chip capacitors are recommended.
V
Bypass to GND with 0.1μF ceramic chip capacitors.
A
A
ENC
sampled analog input is held on the rising edge of ENC
Internally biased to 1.6V through a 6.2kΩ resistor. Output
data can be latched on the rising edge of ENC
ENC
sampled analog input is held on the falling edge of ENC
Internally biased to 1.6V through a 6.2kΩ resistor. By-
pass to ground with a 0.1μF capacitor for a single-ended
Encode signal.
SHDN (Pin 19): Power Shutdown Pin. SHDN = low results
in normal operation. SHDN = high results in powered
down analog circuitry and the digital outputs are set in
high impedance state.
DITH (Pin 20): Internal Dither Enable Pin. DITH = low
disables internal dither. DITH = high enables internal dither.
Refer to Internal Dither section of the data sheet for details
on dither operation.
CM
DD
IN
IN
+
–
(Pin 3): 1.25V Output. Optimum voltage for input com-
+
–
P-P
(Pins 5, 6, 15, 16, 17): 3.3V Analog Supply Pin.
(Pin 8): Positive Differential Analog Input.
(Pin 9): Negative Differential Analog Input.
(Pin 13): Negative Differential Encode Input. The
(Pin 12): Positive Differential Encode Input. The
.
DD
to select the internal
+
.
P-P
+
–
.
.
.
NC (Pins 21, 22): No Connect.
NC (Pins 23, 24): Do Not Connect in LVDS Mode.
D0
51-58): LVDS Digital Outputs. All LVDS outputs require
differential 100Ω termination resistors at the LVDS receiver.
D13
OGND (Pins 31 and 50): Output Driver Ground.
OV
Drivers. Bypass to ground with 0.1μF capacitor.
CLKOUT
0utput. Latch data on the rising edge of CLKOUT
edge of CLKOUT
OF
put OF is high when an over or under fl ow has occurred.
LVDS (Pin 61): Data Output Mode Select Pin. Connecting
LVDS to 0V selects full rate CMOS mode. Connecting LVDS
to 1/3V
LVDS to 2/3V
ing LVDS to V
MODE (Pin 62): Output Format and Clock Duty Cycle
Stabilizer Selection Pin. Connecting MODE to 0V selects
offset binary output format and disables the clock duty
cycle stabilizer. Connecting MODE to 1/3V
binary output format and enables the clock duty cycle sta-
bilizer. Connecting MODE to 2/3V
output format and enables the clock duty cycle stabilizer.
Connecting MODE to V
format and disables the clock duty cycle stabilizer.
RAND (Pin 63): Digital Output Randomization Selection Pin.
RAND low results in normal operation. RAND high selects
D1-D13 to be EXCLUSIVE-ORed with D0 (the LSB). The
output can be decoded by again applying an XOR operation
between the LSB and all other bits. The mode of operation
reduces the effects of digital output interference.
PGA (Pin 64): Programmable Gain Amplifi er Control Pin. Low
selects a front-end gain of 1, input range of 2.25V
selects a front-end gain of 1.5, input range of 1.5V
GND (Exposed Pad Pin 65): ADC Power Ground. The
exposed pad on the bottom of the package must be sol-
dered to ground.
–
–
DD
/OF
/D0
+
/D13
(Pins 32 and 49): Positive Supply for the Output
DD
+
+
–
(Pins 59 and 60): Overfl ow/Underfl ow Digital Out-
to D13
/CLKOUT
selects demultiplexed CMOS mode. Connecting
–
is the MSB.
DD
DD
selects Low Power LVDS mode. Connect-
–
–
selects Standard LVDS mode.
/D13
.
+
(Pins 39 and 40): LVDS Data Valid
+
DD
(Pins 25-30, 33-38, 41-48 and
selects 2’s complement output
DD
LTC2208-14
selects 2’s complement
DD
selects offset
P-P
+
15
, falling
. High
P-P
220814fb
.