AD9237BCPZ-20 Analog Devices Inc, AD9237BCPZ-20 Datasheet - Page 20

• Manufacturer Part Number: AD9237BCPZ-20
• Description: IC ADC 12BIT SGL 20MSPS 32LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD9237BCPZ-20

• Data Interface: Parallel
• Number Of Bits: 12
• Sampling Rate (per Second): 20M
• Number Of Converters: 3
• Power Dissipation (max): 85mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-VFQFN, CSP Exposed Pad
• Resolution (bits): 12bit
• Input Channel Type: Differential
• Supply Voltage Range - Analogue: 2.7V To 3.6V
• Supply Voltage Range - Digital: 2.25V To 3.6V
• Supply Current: 30.5mA
• Sampling Rate: 20MSPS
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9237
This maximum current occurs when every output bit switches
on every clock cycle, that is, a full-scale square wave at the
Nyquist frequency, f
established by the average number of output bits switching,
which is determined by the encode rate and the characteristics
of the analog input signal.
For the AD9237-20 speed grade, the digital power consumption
can represent as much as 10% of the total dissipation. Digital
power consumption can be minimized by reducing the
capacitive load presented to the output drivers. The data in
Figure 43 was taken with a 5 pF load on each output driver.
The AD9237 is designed to provide excellent performance with
minimum power. The analog circuitry is optimally biased so
that each speed grade provides excellent performance while
affording reduced power consumption. Each speed grade
dissipates a baseline power at low sample rates that increases
linearly with the clock frequency, as shown in Figure 43.
The power scaling feature provides an additional power savings
when enabled, as shown in Figure 44. The power scaling mode
cannot be enabled if the clock is varied during operation. This is
because the internal circuitry cannot quickly track a changing
clock, and the part does not have enough power to operate
properly.
190
170
150
130
110
90
70
Figure 43. Total Power vs. Sample Rate with f
10
AD9237-65
AD9237-40
AD9237-20
20
CLK
/2. In practice, the DRVDD current is
SAMPLE RATE (MSPS)
30
40
50
IN
= 10 MHz
60
65
Rev. A | Page 20 of 24
The MODE2 pin is a multilevel input that controls the span
factor and power scaling modes. The MODE2 pin is internally
pulled down to AGND by a 70 kΩ resistor. The input threshold
and corresponding mode selections are outlined in Table 8.
Table 8. MODE2 Selection
MODE2 Voltage
AVDD
2/3 AVDD
1/3 AVDD
AGND (Default)
The PDWN pin is a multilevel input that controls the power
states. The input threshold values and corresponding power
states are outlined in Table 9.
Table 9. PDWN Selection
PDWN Voltage
AVDD
1/3 AVDD
AGND (Default)
By asserting the PDWN pin high, the AD9237 is placed in
power-down mode. In this state, the ADC typically dissipates
1 mW. During power-down, the output drivers are placed in a
high impedance state. Low power dissipation in power-down
mode is achieved by shutting down the reference, reference
buffer, biasing networks, clock, and duty cycle stabilizer
circuitry. The decoupling capacitors on REFT and REFB are
discharged when entering power-down mode and then must
be recharged when returning to normal operation.
As a result, the wake-up time is related to the time spent
in power-down mode and shorter standby cycles result in
proportionally shorter wake-up times. With the recommended
0.1 μF and 10 μF decoupling capacitors on REFT and REFB, it
takes approximately 1 sec to fully discharge the reference buffer
decoupling capacitors and 3 ms to restore full operation.
Figure 44. Total Power vs. Sample Rate with Power Scaling Enabled
190
170
150
130
110
90
70
10
AD9237-20
Power State
Power-Down Mode
Standby Mode
Normal Operation
AD9237-40
20
Span Factor
1
1
2
2
SAMPLE RATE (MSPS)
30
40
Power Scaling
Disabled
Enabled
Enabled
Disabled
Power (mW)
1
20
Based on speed grade
50
AD9237-65
60
65