KAD5512P-25Q48 Intersil, KAD5512P-25Q48 Datasheet - Page 24

• Manufacturer Part Number: KAD5512P-25Q48
• Description: IC ADC 12BIT 250MSPS SGL 48-QFN
• Manufacturer: Intersil
• Series: FemtoCharge™r

Specifications of KAD5512P-25Q48

• Number Of Bits: 12
• Sampling Rate (per Second): 250M
• Data Interface: Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 286mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-VQFN
• For Use With: KDC5512-Q48EVAL - DAUGHTER CARD FOR KAD5512KDC5512EVAL - DAUGHTER CARD FOR KAD5512
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Serial Peripheral Interface
A serial peripheral interface (SPI) bus is used to
facilitate configuration of the device and to optimize
performance. The SPI bus consists of chip select (CSB),
serial clock (SCLK) serial data output (SDO), and serial
data input/output (SDIO). The maximum SCLK rate is
equal to the ADC sample rate (f
for write operations and f
reads. At f
15.63MHz for writing and 3.79MHz for read operations.
There is no minimum SCLK rate.
The following sections describe various registers that
are used to configure the SPI or adjust performance or
functional parameters. Many registers in the available
address space (0x00 to 0xFF) are not defined in this
document. Additionally, within a defined register there
may be certain bits or bit combinations that are
reserved. Undefined registers and undefined values
within defined registers are reserved and should not be
selected. Setting any reserved register or value may
produce indeterminate results.
SPI Physical Interface
The serial clock pin (SCLK) provides synchronization for
the data transfer. By default, all data is presented on the
serial data input/output (SDIO) pin in three-wire mode.
The state of the SDIO pin is set automatically in the
communication protocol (described below). A dedicated
serial data output pin (SDO) can be activated by setting
0x00[7] high to allow operation in four-wire mode.
SDO should always be connected to OVDD with a 4.7kΩ
resistor even if not used. If the 4.7kΩ resistor is not
present the ADC will not exit the reset state.
The SPI port operates in a half duplex master/slave
configuration, with the KAD5512P functioning as a slave.
Multiple slave devices can interface to a single master in
three-wire mode only, since the SDO output of an
unaddressed device is asserted in four-wire mode.
The chip-select bar (CSB) pin determines when a slave
device is being addressed. Multiple slave devices can be
written to concurrently, but only one slave device can be
read from at a given time (again, only in three-wire
mode). If multiple slave devices are selected for reading
at the same time, the results will be indeterminate.
The communication protocol begins with an
instruction/address phase. The first rising SCLK edge
SCLK
SDIO
CSB
SAMPLE
= 250MHz, maximum SCLK is
INSTRUCTION/ADDRESS
SAMPLE
24
SAMPLE
divided by 66 for
) divided by 16
FIGURE 40. N-BYTE TRANSFER
KAD5512P
CSB STALLING
LAST LEGAL
DATA WORD 1
following a high to low transition on CSB determines the
beginning of the two-byte instruction/address command;
SCLK must be static low before the CSB transition. Data
can be presented in MSB-first order or LSB-first order.
The default is MSB-first, but this can be changed by
setting 0x00[6] high. Figures 35 and 36 show the
appropriate bit ordering for the MSB-first and LSB-first
modes, respectively. In MSB-first mode the address is
incremented for multi-byte transfers, while in LSB-first
mode it’s decremented.
In the default mode, the MSB is R/W, which determines if
the data is to be read (active high) or written. The next
two bits, W1 and W0, determine the number of data
bytes to be read or written (see Table 6). The lower 13
bits contain the first address for the data transfer. This
relationship is illustrated in Figure 37, and timing values
are given in “Switching Specifications” on page 14.
After the instruction/address bytes have been read, the
appropriate number of data bytes are written to or read
from the ADC (based on the R/W bit status). The data
transfer will continue as long as CSB remains low and
SCLK is active. Stalling of the CSB pin is allowed at any
byte boundary (instruction/address or data) if the
number of bytes being transferred is three or less. For
transfers of four bytes or more, CSB is allowed stall in
the middle of the instruction/address bytes or before the
first data byte. If CSB transitions to a high state after
that point the state machine will reset and terminate the
data transfer.
Figures 39 and 40 illustrate the timing relationships for
2-byte and N-byte transfers, respectively. The operation for
a 3-byte transfer can be inferred from these diagrams.
SPI Configuration
ADDRESS 0X00: CHIP_PORT_CONFIG
Bit ordering and SPI reset are controlled by this register. Bit
order can be selected as MSB to LSB (MSB first) or LSB to
MSB (LSB first) to accommodate various microcontrollers.
TABLE 6. BYTE TRANSFER SELECTION
[W1:W0]
00
01
10
11
DATA WORD N
BYTES TRANSFERRED
4 or more
1
2
3
October 1, 2010
FN6807.4