AD7719BR Analog Devices Inc, AD7719BR Datasheet - Page 13

• Manufacturer Part Number: AD7719BR
• Description: IC ADC 16BIT 24BIT DUAL 28-SOIC
• Manufacturer: Analog Devices Inc

Specifications of AD7719BR

• Number Of Bits: 16/24
• Sampling Rate (per Second): 105
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 2
• Power Dissipation (max): 4.5mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (0.300", 7.50mm Width)
• For Use With: EVAL-AD7719EB - BOARD EVAL FOR AD7719
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Both Channels
The operation of the aux channel is identical to the main
channel with the exception that there is no PGA on the aux
channel. The input chopping is incorporated into the input
multiplexer while the output chopping is accomplished by an
XOR gate at the output of the modulator. The chopped modulator
bit stream is applied to a Sinc
Sinc
actual decimation factor is the register value times 8. The
decimated output rate from the Sinc
conversion rate) will therefore be
where:
f
SF is the decimal equivalent of the word loaded to the
filter register.
f
Programming the filter register determines the update rate for
both the main and aux ADC. Both ADCs operate with the same
update rate.
The chop rate of the channel is half the output data rate.
The frequency response of the filter H (f) is as follows:
where:
f
SF = value programmed into SF SFR.
f
The following shows plots of the filter frequency response for
the SF words shown in Table I. The overall frequency response
is the product of a Sinc
notches at integer multiples of 3 × f
REV. A
ADC
MOD



MOD
OUT
SF
3
1
is the ADC update rate.
= f
is the modulator sampling rate of 32.768 kHz.
×
= 32,768 Hz
decimation factor is restricted to an 8-bit register SF; the
ANALOG
8
MOD
INPUT
×
sin (
/(SF × 8 × 3)
SF
sin (
× × ×
f
π
ADC
f
MUX
8
CHOP
×
f f
π
3
/
=
and a sinc response. There are Sinc
MOD
1
3
f f
/
×
)
MOD
3



8
filter. The programming of the
×
)
1
SF
ADC

 ×

3
3

 ×

and there are sinc notches



filter (and the ADC
Figure 5. Auxiliary ADC Channel Block Diagram
1
2
f
×
MOD
sin (
sin (
2
× ×
π
MOD1
f
MOD
π
×
-
f f
/
f f
/
OUT
OUT
)
3
)
f
CHOP
XOR



–13–
at odd integer multiples of f
values of SF obeys the following equation:
The signal chain is chopped as shown in Figures 4 and 5. The
chop frequency is
As shown in the block diagram, the Sinc
contain +V
offset. This offset is removed by performing a running average
of 2. This average by 2 means that the settling time to any change
in programming of the ADC will be twice the normal conversion
time, while an asynchronous step change on the analog input will
not be fully reflected until the third subsequent output.
The allowable range for SF is 13 to 255, with a default of 69
(0x45). The corresponding conversion rates, conversion times,
and settling times are tabulated in Table I. Note that the con-
version time increases by 0.732 ms for each increment in SF.
SF
Word
13
69 (Default)
255
Normal mode rejection is the major function of the digital filter
on the AD7719. The normal mode 50 Hz ± 1 Hz rejection with an
SF word of 82 is typically –100 dB. The 60 Hz ± 1 Hz rejec-
tion with SF = 68 is typically –100 dB. Simultaneous 50 Hz and
60 Hz rejection of better than 60 dB is achieved with an SF of
69. Choosing an SF word of 69 places notches at both 50 Hz
and 60 Hz. Figures 6 to 9 show the filter rejection for a selec-
tion of SF words.
Table I. ADC Conversion and Settling Times for Various
SF Words
(
8
1
SF
OS
)
3
SINC
and –V
3
t
FILTER
SETTLE
Data Update Rate
f
105.3
19.79
5.35
f
ADC
OS
(
3
, where V
3
f
CHOP
dB
(Hz)
=
(8



ADC
)
f
=
ADC
SF )
=
2
0 24
/2. The 3 dB frequency for all



.
A
A
OS

 = ×

IN
f
IN
f
ADC
ADC
2
– V
+ V
is the respective channel
×
2
3
OS
OS



f
filter outputs alternately
ADC
1
2
t
ADC
AD7719
Settling Time
t
19.04
373.54
101.07
SETTLE
DIGITAL
OUTPUT
(ms)