AD7719BR Analog Devices Inc, AD7719BR Datasheet - Page 8

• Manufacturer Part Number: AD7719BR
• Description: IC ADC 16BIT 24BIT DUAL 28-SOIC
• Manufacturer: Analog Devices Inc

Specifications of AD7719BR

• Number Of Bits: 16/24
• Sampling Rate (per Second): 105
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 2
• Power Dissipation (max): 4.5mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (0.300", 7.50mm Width)
• For Use With: EVAL-AD7719EB - BOARD EVAL FOR AD7719
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

AD7719
DIGITAL INTERFACE
As previously outlined, the AD7719’s programmable functions are
controlled using a set of on-chip registers. Data is written to these
registers via the part’s serial interface; read access to the on-chip
registers is also provided by this interface. All communications to
the part must start with a write operation to the Communications
register. After power-on or RESET, the device expects a write to
its Communications register. The data written to this register
determines whether the next operation to the part is a read or a
write operation and also determines to which register this read
or write operation occurs. Therefore, write access to any of the
other registers on the part starts with a write operation to the
Communications register followed by a write to the selected
register. A read operation from any other register on the part
(including the output data register) starts with a write operation
to the Communications register followed by a read operation
from the selected register.
The AD7719’s serial interface consists of five signals: CS, SCLK,
DIN, DOUT, and RDY. The DIN line is used for transferring
data into the on-chip registers while the DOUT line is used for
accessing data from the on-chip registers. SCLK is the serial
clock input for the device, and all data transfers (either on DIN
or DOUT) take place with respect to this SCLK signal. The
RDY line is used as a status signal to indicate when data is ready
to be read from the AD7719’s data register. RDY goes low when a
new data-word is available in the output register of either the
main or aux ADCs. It is reset high when a read operation from
the data register is complete. It also goes high prior to the updating
DOUT
SCLK
RDY
SCLK
CS
DIN
CS
t
3
t
11
t
t
4
5A
t
12
t
MSB
MSB
5
t
13
Figure 2. Write Cycle Timing Diagram
Figure 3. Read Cycle Timing Diagram
t
14
t
6
t
15
t
7
–8–
of the output register to indicate when not to read from the device
to ensure that a data read is not attempted while the register is
being updated. CS is used to select the device. It can be used to
decode the AD7719 in systems where a number of parts are
connected to the serial bus.
Figures 2 and 3 show timing diagrams for interfacing to the
AD7719 with CS used to decode the part. Figure 3 is for a read
operation from the AD7719’s output shift register while Figure 2
shows a write operation to the input shift register. It is possible
to read the same data twice from the output register even though
the RDY line returns high after the first read operation. Care must
be taken, however, to ensure that the read operations have been
completed before the next output update is about to take place.
The AD7719 serial interface can operate in 3-wire mode by tying
the CS input low. In this case, the SCLK, DIN, and DOUT lines
are used to communicate with the AD7719, and the status of
RDY bits (RDY0 and RDY1) can be obtained by interrogating
the STATUS register. This scheme is suitable for interfacing to
microcontrollers. If CS is required as a decoding signal, it can
be generated from a port bit. For microcontroller interfaces, it is
recommended that the SCLK idles high between data transfers.
The AD7719 can also be operated with CS used as a frame syn-
chronization signal. This scheme is suitable for DSP interfaces.
In this case, the first bit (MSB) is effectively clocked out by CS
since CS would normally occur after the falling edge of SCLK
in DSPs. The SCLK can continue to run between data transfers
provided the timing numbers are obeyed.
t
6
LSB
LSB
t
10
t
t
16
8
t
9
REV. A