LTC1292DCN8#PBF Linear Technology, LTC1292DCN8#PBF Datasheet - Page 16

• Manufacturer Part Number: LTC1292DCN8#PBF
• Description: IC DATA ACQ SYSTEM 12BIT 8-DIP
• Manufacturer: Linear Technology
• Type: Data Acquisition System (DAS)r

Specifications of LTC1292DCN8#PBF

• Resolution (bits): 12 b
• Sampling Rate (per Second): 60k
• Data Interface: Serial, Parallel
• Voltage Supply Source: Single Supply
• Voltage - Supply: 5V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 8-DIP (0.300", 7.62mm)
• Number Of Elements: 1
• Resolution: 12Bit
• Architecture: SAR
• Sample Rate: 60KSPS
• Input Polarity: Unipolar
• Input Type: Voltage
• Rated Input Volt: 5V
• Differential Input: Yes
• Power Supply Requirement: Single
• Single Supply Voltage (typ): 5V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Power Dissipation: 500mW
• Integral Nonlinearity Error: ±0.75LSB
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 8
• Package Type: PDIP N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LTC1292/LTC1297
A
“–” input voltage be free of noise and settle completely
during the first CLK cycle of the conversion. Minimizing
R
input source resistance must be used the time can be
extended by using a slower CLK frequency. At the maximum
CLK frequency of 1MHz, R
will provide adequate settling.
Input Op Amps
When driving the analog inputs with an op amp it is
important that the op amp settles within the allowed time
(see Figures 11a, 11b, 11c and 12). Again the “+” and “–
” input sampling times can be extended as described
above to accommodate slower op amps. Most op amps
including the LT1797 and LT1677 single supply op amps
can be made to settle well even with the minimum settling
windows of 3.0 s for the LTC1292 or 6.0 s for the
LTC1297 (“+” input) and 1 s (“–” input) that occurs at the
maximum clock rate of 1MHz. Figures 13 and 14 show
examples of both adequate and poor op amp settling.
16
SOURCE
PPLICATI
– and C2 will improve settling time. If large “–”
(–) INPUT
(+) INPUT
D
CLK
O
OUT
CS
U
S
SOURCE
I FOR ATIO
U
Figure 12. “+” and “–” Input Settling Windows for the LTC1297
– < 250 and C2 < 20pF
W
t
WHCS
U
HI-Z
(+) INPUT MUST SETTLE
DURING THIS TIME
t
suCS
Figure 13. Adequate Settling of Op Amp Driving Analog Input
t
Figure 14. Poor Op Amp Settling Can Cause A/D Errors
SMPL
1ST BIT TEST (–) INPUT MUST
SETTLE DURING THIS TIME
HORIZONTAL: 20 s/DIV
HORIZONTAL: 500ns/DIV
B11
LTC1292/7 F12
B10
12927fb