ISL90726UIE627Z-TK Intersil, ISL90726UIE627Z-TK Datasheet - Page 4

• Manufacturer Part Number: ISL90726UIE627Z-TK
• Description: IC POT DGTL 50K OHM SC70-6
• Manufacturer: Intersil
• Series: XDCP™r

Specifications of ISL90726UIE627Z-TK

• Taps: 128
• Resistance (ohms): 50K
• Number Of Circuits: 1
• Temperature Coefficient: 45 ppm/°C Typical
• Memory Type: Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: SC-70-6, SC-88, SOT-363
• Resistance In Ohms: 50K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISL90726UIE627Z-TKTR

Operating Specifications
SERIAL INTERFACE SPECIFICATIONS
V
Cpin (Note 9)
V
t
t
R
IH
Hysteresis
F
IL
SYMBOL
t
t
t
t
t
t
HD:STO
HD:STA
SU:DAT
HD:DAT
SU:STO
(Note 11)
(Note 11)
SU:STA
(Note 10)
t
(Note 10)
t
f
t
HIGH
V
LOW
t
SCL
t
BUF
t
DH
t
AA
IN
OL
D
Power-up Delay
SDA, and SCL Input Buffer LOW
Voltage
SDA, and SCL Input Buffer
HIGH Voltage
SDA and SCL Input Buffer
Hysteresis
SDA Output Buffer LOW
Voltage, Sinking 4mA
SDA, and SCL Pin Capacitance
SCL Frequency
Pulse Width Suppression Time
at SDA and SCL Inputs
SCL Falling Edge to SDA Output
Data Valid
Time the Bus Must be Free
Before the Start of a New
Transmission
Clock LOW Time
Clock HIGH Time
START Condition Setup Time
START Condition Hold Time
Input Data Setup Time
Input Data Hold Time
STOP Condition Setup Time
STOP Condition Hold Time for
Read, or Volatile Only Write
Output Data Hold Time
SDA and SCL Rise Time
SDA and SCL Fall Time
PARAMETER
4
(Continued)
V
recall completed, and I
state
Any pulse narrower than the max spec is
suppressed.
SCL falling edge crossing 30% of V
SDA exits the 30% to 70% of V
SDA crossing 70% of V
condition, to SDA crossing 70% of V
the following START condition.
Measured at the 30% of V
Measured at the 70% of V
SCL rising edge to SDA falling edge. Both
crossing 70% of V
From SDA falling edge crossing 30% of V
SCL falling edge crossing 70% of V
From SDA exiting the 30% to 70% of V
window, to SCL rising edge crossing 30% of
V
From SCL rising edge crossing 70% of V
SDA entering the 30% to 70% of V
From SCL rising edge crossing 70% of V
SDA rising edge crossing 30% of V
From SDA rising edge to SCL falling edge. Both
crossing 70% of V
From SCL falling edge crossing 30% of V
until SDA enters the 30% to 70% of V
window.
From 30% to 70% of V
From 70% to 30% of V
CC
CC
above V
POR
TEST CONDITIONS
ISL90726
, to DCP Initial Value Register
CC
CC
.
.
2
CC
CC
C Interface in standby
CC
CC
CC
during a STOP
crossing.
crossing.
CC
window.
CC
CC
CC
CC
CC
CC
.
window.
, until
.
CC
during
CC
CC
CC
CC
, to
,
to
to
(Note 12)
0.05*V
0.7*V
0.1*Cb
0.1*Cb
1300
1300
20 +
20 +
MIN
-0.3
600
600
600
100
600
600
0
0
0
CC
CC
(Note 2)
TYP
V
(Note 12) UNIT
0.3*V
CC
MAX
400
900
250
250
0.4
10
50
3
+ 0.3
August 26, 2008
CC
FN8244.4
kHz
ms
pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
V
V
V
V