ISL90726UIE627Z-TK Intersil, ISL90726UIE627Z-TK Datasheet - Page 6

• Manufacturer Part Number: ISL90726UIE627Z-TK
• Description: IC POT DGTL 50K OHM SC70-6
• Manufacturer: Intersil
• Series: XDCP™r

Specifications of ISL90726UIE627Z-TK

• Taps: 128
• Resistance (ohms): 50K
• Number Of Circuits: 1
• Temperature Coefficient: 45 ppm/°C Typical
• Memory Type: Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: SC-70-6, SC-88, SOT-363
• Resistance In Ohms: 50K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISL90726UIE627Z-TKTR

I
The ISL90726 supports bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter and the receiving device as the receiver.
The device controlling the transfer is a master and the
device being controlled is the slave. The master always
initiates data transfers and provides the clock for both
transmit and receive operations. Therefore, the ISL90726
operates as slave device in all applications.
All communication over the I
sending the MSB of each byte of data first.
Protocol Conventions
Data states on the SDA line can change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating START and STOP conditions (see
Figure 1). On power-up of the ISL90726, the SDA pin is in
the input mode.
All I
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH. The ISL90726 continuously monitors the SDA
and SCL lines for the START condition and does not
respond to any command until this condition is met (see
Figure 1). A START condition is ignored during the power-up
sequence and during internal non-volatile write cycles.
All I
condition, which is a LOW to HIGH transition of SDA while
SCL is HIGH (see Figure 1).
An ACK, Acknowledge, is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, releases the SDA bus after
transmitting eight bits. During the ninth clock cycle, the
receiver pulls the SDA line LOW to acknowledge the
reception of the eight bits of data (see Figure 2).
The ISL90726 responds with an ACK after recognition of a
START condition followed by a valid Identification Byte, and
once again after successful receipt of an Address Byte. The
ISL90726 also responds with an ACK after receiving a Data
Byte of a write operation. The master must respond with an
ACK after receiving a Data Byte of a read operation.
2
C Serial Interface
2
2
C interface operations must begin with a START
C interface operations must be terminated by a STOP
SDA
SCL
2
C interface is conducted by
6
FIGURE 1. VALID DATA CHANGES, START, AND STOP CONDITIONS
START
STABLE
DATA
ISL90726
CHANGE
DATA
A valid Identification Byte contains 0101110 as the seven
MSBs. The LSB in the Read/Write bit. Its value is “1” for a
Read operation, and “0” for a Write operation (see Table 1).
Write Operation
A Write operation requires a START condition, followed by a
valid Identification Byte, a valid Address Byte, a Data Byte,
and a STOP condition. After each of the three bytes, the
ISL90726 responds with an ACK. At this time, the device
enters its standby state (see Figure 3).
Data Protection
A valid Identification Byte, Address Byte, and total number of
SCL pulses act as a protection of both volatile and non-
volatile registers. During a Write sequence, the Data Byte is
loaded into an internal shift register as it is received. If the
Address Byte is 0h, the Data Byte is transferred to the Wiper
Register (WR) at the falling edge of the SCL pulse that loads
the last bit (LSB) of the Data Byte. If an address other than
00h, or an invalid slave address is sent, then the device will
respond with no ACK.
Read Operation
A Read operation consist of a three byte instruction followed
by one or more Data Bytes (see Figure 4). The master
initiates the operation issuing the following sequence: a
START, the Identification byte with the R/W bit set to “0”, an
Address Byte, a second START, and a second Identification
byte with the R/W bit set to “1”. After each of the three bytes,
the ISL90726 responds with an ACK. Then the ISL90726
transmits the Data Byte as long as the master responds with
an ACK during the SCL cycle following the eighth bit of each
byte. The master then terminates the read operation (issuing
a STOP condition) following the last bit of the Data Byte
(see Figure 4).
(MSB)
0
STABLE
DATA
TABLE 1. IDENTIFICATION BYTE FORMAT
1
0
1
STOP
1
1
0
August 26, 2008
FN8244.4
(LSB)
R/W