IDTV104YLF IDT, Integrated Device Technology Inc, IDTV104YLF Datasheet

IDTV104YLF

Manufacturer Part Number

IDTV104YLF

Description

Manufacturer

IDT, Integrated Device Technology Inc

Datasheet

1.IDTV104YLF.pdf (11 pages)

Specifications of IDTV104YLF

Number Of Elements

Number Of Receivers

Input Type

CMOS/TTL

Operating Supply Voltage (typ)

3.3V

Differential Input High Threshold Voltage

100mV

Diff. Input Low Threshold Volt

-100mV

Power Dissipation

Operating Temperature Classification

Commercial

Mounting

Surface Mount

Pin Count

Lead Free Status / Rohs Status

Compliant

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V104 Datasheet

General Description

The V104 10 Bit LVDS Receiver for Video is designed

to support video data transmission between display

engines and video processing engines for television

and projector applications. The V104 supports up to

WXGA resolutions for Plasma, Rear Projection, Front

Projection, CRT and LCD applications.

The V104 converts the 6 LVDS (Low Voltage

Differential Signaling) video data stream pairs to 35

CMOS/TTL data bits with a rising or falling edge clock.

The clock edge selection is performed using a

dedicated pin.

In conjunction with the V103 transmitter, the V104 can

transmit 10 bits per color (R, G, B) along with 5 bits of

control and timing data (HSYNC, VSYNC, DE, CNTL1,

CNTL2) over a low EMI, low bus width connection

including connectors and standard LVDS cabling.

Block Diagram

I n t e g r a t e d C i r c u i t S y s t e m s • 5 2 5 R a c e Str e e t , S a n J o s e , C A 9 51 2 6 • t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1 • ww w.i c s t . c o m

V104

10 B

CMOS/TTL Input

(8 to 90 MHz)

RCLK+/-

LVDS Input

TEST

LVDS R

RA+/-

RB+/-

RC+/-

RD+/-

RE+/-

R/F

ECEIVER FOR

Serial to

Parallel

PLL

Features

•

Pin & function compatible with the THC63LVD104A

Wide pixel clock range: 8 - 90 MHz

Guaranteed operation over -20 to +85° C ambient

temperature.

Supports resolutions from 480p to WXGA

Internal PLL does not require external loop filter

Clock edge selection for TTL alignment selectable

Power down mode

Single 3.3V supply

Low power consumption CMOS design

64-pin TQFP lead free package

IDEO

CMOS/TTL Output

RD6-RD0

CLKOUT

RA6-RA0

RB6-RB0

RC6-RC0

RE6-RE0

2/1/07

Revision 3.0

Related parts for IDTV104YLF

IDTV104YLF Summary of contents

Page 1

V104 10 B LVDS R IT General Description The V104 10 Bit LVDS Receiver for Video is designed to support video data transmission between display engines and video processing engines for television and projector applications. The V104 supports up to ...

Page 2

V104 10 B LVDS R IT ECEIVER FOR Pin Assignment GND TEST PD OE R/F RE6 RE5 RE4 VCC RE3 RE2 RE1 RE0 RD6 RD5 GND Pin Descriptions Pin Pin Number Name 50, 49 RA+, RA- 52, 51 RB+, RB- ...

Page 3

V104 10 B LVDS R IT ECEIVER FOR Pin Pin Number Name 10, 11, RE6 ~ RE0 12 TEST R/F 9, 23, 37, 48 VCC 31 CLKOUT 1, 16, 30, ...

Page 4

V104 10 B LVDS R IT ECEIVER FOR External Components The V104 requires no external components. Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the V104. These ratings, which are standard values for ICS ...

Page 5

V104 10 B LVDS R IT ECEIVER FOR Electrical Characteristics VDD=3.3 V ±10%, Ambient temperature -20 to +85°C Parameter CMOS/TTL DC Specifications Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Input Current LVDS Receiver DC Specifications ...

Page 6

V104 10 B LVDS R IT ECEIVER FOR Incremental Pattern (Gray Scale) CLKOUT Rx0 Rx1 Rx2 Rx3 Rx4 Rx5 Rx6 Toggle Pattern (Checker) CLKOUT Rx0 Rx1 Rx2 Rx3 Rx4 Rx5 Rx6 X = ...

Page 7

V104 10 B LVDS R IT ECEIVER FOR Parameter Switching Characteristics CLKOUT Period CLK IN High Time CLK IN Low Time TTL Data Setup to CLKOUT TTL Data Hold from CLKOUT TTL Low to High Transition Time TTL High to ...

Page 8

V104 10 B LVDS R IT ECEIVER FOR AC Timing Diagrams TTL Outputs CLK OUT Phase Lock Loop Set Time RCLK+/- CLKOUT V104 Datasheet ...

Page 9

V104 10 B LVDS R IT ECEIVER FOR Power Up Sequence Sequence 1 VCC PVCC LVCC Sequence 2 VCC PVCC LVCC V104 Datasheet ...

Page 10

V104 10 B LVDS R IT ECEIVER FOR LVDS Inputs Rx6 Rx5 Rx+/- RCLK LVDS Inputs RCLK+ (Differential RA+/- RB+/- RC+/- RD+/- RE+/- Previous Cycle t RIP1 V104 Datasheet ...

Page 11

V104 10 B LVDS R IT ECEIVER FOR Package Outline and Package Dimensions Package dimensions are kept current with JEDEC Publication No. 95, variation ACD. ALL DIMENSIONS ARE IN MILLIMETERS. Ordering Information Part / Order Number Marking V104YLF V104YLF V104YLFT ...

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