MT16JTF25664AZ-1G4F1 Micron Technology Inc, MT16JTF25664AZ-1G4F1 Datasheet - Page 8

• Manufacturer Part Number: MT16JTF25664AZ-1G4F1
• Manufacturer: Micron Technology Inc

Specifications of MT16JTF25664AZ-1G4F1

• Main Category: DRAM Module
• Module Type: 240UDIMM
• Device Core Size: 64b
• Organization: 256Mx64
• Total Density: 17179869184
• Number Of Elements: 8
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 240
• Mounting: Socket
• Lead Free Status / Rohs Status: Compliant

General Description
Fly-By Topology
Serial Presence-Detect EEPROM Operation
PDF: 09005aef837cdd2d/Source: 09005aef837cdc74
JTF16C_256_512x64AZ.fm - Rev. A 2/09 EN
The MT16JTF25664AZ and MT16JTF51264AZ DDR3 SDRAM modules are high-speed,
CMOS, dynamic random-access 2GB and 4GB memory modules organized in a x64
configuration. These DDR3 SDRAM modules use internally configured 8-bank 1Gb and
2Gb DDR3 SDRAM devices.
DDR3 SDRAM modules use double data rate architecture to achieve high-speed opera-
tion. The double data rate architecture is essentially an 8n-prefetch architecture with an
interface designed to transfer two data words per clock cycle at the I/O pins. A single
read or write access for the DDR3 SDRAM module effectively consists of a single
8n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and eight corre-
sponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins.
The differential data strobe (DQS, DQS#) is transmitted externally, along with data, for
use in data capture at the DDR3 SDRAM input receiver. DQS is center-aligned with data
for WRITEs. The read data is transmitted by the DDR3 SDRAM and edge-aligned to the
data strobes.
DDR3 SDRAM modules operate from a differential clock (CK and CK#); the crossing of
CK going HIGH and CK# going LOW will be referred to as the positive edge of CK.
Control, command, and address signals are registered at every positive edge of CK. Input
data is registered on both edges of DQS, and output data is referenced to both edges of
DQS, as well as to both edges of CK.
These DDR3 modules use faster clock speeds than earlier DDR technologies, making
signal quality more important than ever. For improved signal quality, the clock, control,
command, and address buses have been routed in a fly-by topology, where each clock,
control, command, and address pin on each DRAM is connected to a single trace and
terminated (rather than a tree structure, where the termination is off the module near
the connector). Inherent to fly-by topology, the timing skew between the clock and DQS
signals can be easily accounted for by using the write-leveling feature of DDR3.
DDR3 SDRAM modules incorporate serial presence-detect. The SPD data is stored in a
256-byte EEPROM. The first 128 bytes are programmed by Micron to comply with JEDEC
standard JC-45 “Appendix X: Serial Presence Detect (SPD) for DDR3 SDRAM Modules.”
These bytes identify module-specific timing parameters, configuration information, and
physical attributes. User-specific information can be written into the remaining
128 bytes of storage. READ/WRITE operations between the master (system logic) and
the slave EEPROM device occur via a standard I
SDA (data) signals, together with SA[2:0], which provide eight unique DIMM/EEPROM
addresses. Write protect (WP) is connected to Vss, permanently disabling hardware
write protection.
2GB, 4GB (x64, DR): 240-Pin DDR3 SDRAM UDIMM
8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2
C bus using the DIMM’s SCL (clock) and
General Description
©2008 Micron Technology, Inc. All rights reserved.