ISP1564HLUM STEricsson, ISP1564HLUM Datasheet
ISP1564HLUM
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ISP1564HLUM Summary of contents
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IMPORTANT NOTICE Dear customer from August 2 2008, the wireless operations of NXP have moved to a new company, ST-NXP Wireless result, the following changes are applicable to the attached document. ● Company name - NXP ...
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ISP1564 Hi-Speed Universal Serial Bus PCI Host Controller Rev. 01 — 4 December 2006 1. General description The ISP1564 is a Peripheral Component Interconnect (PCI)-based, single-chip Universal Serial Bus (USB) Host Controller. It integrates one Original USB Open Host Controller ...
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NXP Semiconductors I Supports PCI 32-bit, 33 MHz interface compliant with PCI Local Bus Specification Rev. 2.2 , with support for D3 standard I Compliant with PCI Bus Power Management Interface Specification Rev. 1.1 for all hosts (EHCI and OHCI), ...
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PME# CLK 22, 32 AD[31: 31, 33, 34 54, 56, 57, PCI CORE 59, 62, 63 C/BE[3:0]# 23, 35, 48, 60 REQ# 9 PCI MASTER ...
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NXP Semiconductors 6. Pinning information 6.1 Pinning 1 GNDA AUX(1V8 CC(AUX) 4 INTA# 5 RST# SYS_TUNE 6 CLK 7 8 GNT# REQ# 9 AD[31 CC(IO) 12 AD[30] AD[29] 13 AD[28 AD[27] 16 ...
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NXP Semiconductors Fig 3. Pin configuration TFBGA100 (top view) 6.2 Pin description Table 2. Pin description [1] Symbol Pin LQFP100 TFBGA100 GNDA 1 B1 AUX(1V8 CC(AUX) INTA RST SYS_TUNE 6 C6 ...
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NXP Semiconductors Table 2. Pin description …continued [1] Symbol Pin LQFP100 TFBGA100 AD[29 AD[28 AD[27 CC(REG) GNDA 17 G1 REG(1V8 GND 19 F4 AD[26 AD[25 ...
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NXP Semiconductors Table 2. Pin description …continued [1] Symbol Pin LQFP100 TFBGA100 C/BE[2 FRAME IRDY TRDY DEVSEL CC(IO) STOP CLKRUN REG(1V8 ...
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NXP Semiconductors Table 2. Pin description …continued [1] Symbol Pin LQFP100 TFBGA100 AD[11 CC(IO) AD[10 AD[ REG(1V8 AD[8] 59 F10 C/BE[0 GNDA 61 G10 AD[ ...
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NXP Semiconductors Table 2. Pin description …continued [1] Symbol Pin LQFP100 TFBGA100 PWE1_N 79 D7 GND_RREF 80 A8 RREF 81 B8 GNDA 82 C7 DM1 83 A7 GNDA 84 B7 DP1 CCA(AUX) OC2_N 87 E6 ...
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NXP Semiconductors 7. Functional description 7.1 OHCI Host Controller An OHCI Host Controller per port transfers data to devices at the Original USB defined bit rate of 12 Mbit/s or 1.5 Mbit/s. 7.2 EHCI Host Controller The EHCI Host Controller ...
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NXP Semiconductors 7.7 Power-On Reset (POR) Figure 4 start with 1. At t1, the detector passes through the trip level. Another delay will be added before POR drops ensure that the length of the generated detector pulse, ...
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NXP Semiconductors ( (2) This electrolytic or tantalum capacitor must be of LOW ESR type (0.2 (3) The use of ferrite bead is optional. Can be directly tied to ground. (4) This electrolytic or tantalum capacitor is needed ...
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NXP Semiconductors Each function has its own configuration space. The PCI enumerator must allocate the memory address space for each of these functions. Power management is implemented in each PCI function and all power states are provided. This allows the ...
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NXP Semiconductors Table 3. PCI configuration space registers of OHCI and EHCI Address Bits Bits PCI configuration header registers 00h Device ID[15:0] 04h Status[15:0] 08h Class Code[23:0] 0Ch reserved 10h 14h 18h 1Ch 20h ...
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NXP Semiconductors 8.2.1.1 Vendor ID register This read-only register identifies the manufacturer of the device. PCI Special Interest Group (PCI-SIG) assigns valid vendor identifiers to ensure the uniqueness of the identifier. The bit description is shown in Table 4. VID ...
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NXP Semiconductors Table 7. Command register (address 04h) bit description Bit Symbol Description reserved - 9 FBBE Fast Back-to-Back Enable: This bit controls whether a master can do fast back-to-back transactions to various devices. The initialization software ...
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NXP Semiconductors 8.2.1.4 Status register The Status register is a 2-byte read-only register used to record status information on PCI bus-related events. For bit allocation, see Table 8. Status register (address 06h) bit allocation Bit 15 Symbol DPE SSE Reset ...
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NXP Semiconductors Table 9. Status register (address 06h) bit description Bit Symbol Description 5 66MC 66 MHz Capable: This read-only bit indicates whether this device is capable of running at 66 MHz. 0 — 33 MHz 1 — 66 MHz ...
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NXP Semiconductors Table 12. Class Code register (address 09h) bit description Bit Symbol Description BCC[7:0] Base Class Code: 0Ch is the base class code assigned to this byte. It implies a serial bus controller ...
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NXP Semiconductors Table 16. Header Type register (address 0Eh) bit description Bit Symbol Description 7 MFD Multi-Function Device: This bit identifies a multifunction device. 0 — The device has a single function. 1 — The device has multiple functions. 6 ...
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NXP Semiconductors Table 19. SID - Subsystem ID register (address 2Eh) bit description Legend: * reset value Bit Symbol Access SID[15: for OHCI for EHCI. 8.2.1.13 Capabilities Pointer register ...
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NXP Semiconductors 8.2.1.16 Min_Gnt and Max_Lat registers The Minimum Grant (Min_Gnt) and Maximum Latency (Max_Lat) registers are used to specify the desired settings of the device for latency timer values. For both registers, the value specifies a period of time ...
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NXP Semiconductors 8.2.2 Enhanced Host Controller-specific PCI registers In addition to PCI configuration header registers, EHCI needs some additional PCI configuration space registers to indicate the serial bus release number, downstream port wake-up event capability, and adjust the USB bus ...
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NXP Semiconductors Table 29. FLADJ value 0 (00h) 1 (01h) 2 (02h (1Fh) 32 (20h (3Eh) 63 (3Fh) 8.2.2.3 PORTWAKECAP register Port Wake Capability (PORTWAKECAP 2-byte register used to establish a policy about which ...
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NXP Semiconductors Table 32. Cap_ID - Capability Identifier register bit description Address: Value read from address 34h + 0h Legend: * reset value Bit Symbol Access CAP_ID[7:0] R 8.2.3.2 Next_Item_Ptr register The Next Item Pointer (Next_Item_Ptr) register ...
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NXP Semiconductors Table 35. PMC - Power Management Capabilities register bit description Address: Value read from address 34h + 2h Bit Symbol Description PME_S PME Support: These bits indicate the power states in which the function may ...
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NXP Semiconductors 8.2.3.4 PMCSR register The Power Management Control/Status (PMCSR) register is a 2-byte register used to manage the power management state of the PCI function, as well as to allow and monitor Power Management Events (PMEs). The bit allocation ...
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NXP Semiconductors Table 37. PMCSR - Power Management Control/Status register bit description Address: Value read from address 34h + 4h Bit Symbol Description 8 PMEE PME Enabled: Logic 1 allows the function to assert PME#. When it is logic 0, ...
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NXP Semiconductors Table 40. Originating device’s bridge PM state hot D3 cold 8.2.3.6 Data register The Data register is an optional, 1-byte register that provides a mechanism for the function to report state dependent operating data, ...
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NXP Semiconductors Table 44. VPD_Next_Item_Ptr - Vital Product Data Next Item Pointer register bit description Address: Value read from address 34h + 9h Legend: * reset value Bit Symbol Access Value Description VPD_NEXT_ITEM R _PTR[7:0] 8.2.4.3 VPD_Addr ...
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NXP Semiconductors C-bus interface A simple I product ID and some other configuration bits from an external EEPROM. 2 The I C-bus interface is for bidirectional communication between ICs using two serial bus wires: SDA (data) and ...
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NXP Semiconductors The slave address that the ISP1564 uses to access the EEPROM is 101 0000b. Page mode addressing is not supported. Therefore, pins A0, A1 and A2 of the EEPROM must be connected to ground (logic 0). 9.3 Information ...
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NXP Semiconductors B1 state (PCI clock = intermittent clock operation mode, PCI bus power = on) — When a PCI bus is in B1, PCI V transactions, however, are allowed to take place on the bus. The B1 state indicates ...
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NXP Semiconductors 11. USB Host Controller registers Each Host Controller contains a set of on-chip operational registers that are mapped to un-cached memory of the system addressable space. This memory space must begin on a DWORD (32-bit) boundary. The size ...
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NXP Semiconductors Table 48. USB Host Controller registers Address OHCI register 64h reserved 68h reserved 6Ch reserved 70h reserved [1] Reset values that are highlighted, for example, 0, are the ISP1564 implementation-specific reset values; and reset values that are not ...
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NXP Semiconductors Table 50. HcRevision - Host Controller Revision register bit description Address: Content of the base address register + 00h Bit Symbol Description reserved - REV[7:0] Revision: This read-only field contains the BCD ...
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NXP Semiconductors Table 52. HcControl - Host Controller Control register bit description Address: Content of the base address register + 04h Bit Symbol Description reserved - 10 RWE Remote Wake-up Enable: This bit is used by the ...
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NXP Semiconductors Table 52. HcControl - Host Controller Control register bit description Address: Content of the base address register + 04h Bit Symbol Description 4 CLE Control List Enable: This bit is set to enable the processing of the control ...
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NXP Semiconductors Bit 23 Symbol Reset 0 Access R/W R/W Bit 15 Symbol Reset 0 Access R/W R/W Bit 7 Symbol Reset 0 Access R/W R/W [1] The reserved bits must always be written with the reset value. Table 54. ...
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NXP Semiconductors Table 54. HcCommandStatus - Host Controller Command Status register bit description Address: Content of the base address register + 08h Bit Symbol Description 2 BLF Bulk List Filled: This bit is used to indicate whether there are any ...
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NXP Semiconductors Bit 7 [1] Symbol reserved RHSC Reset 0 Access R/W R/W [1] The reserved bits must always be written with the reset value. Table 56. HcInterruptStatus - Host Controller Interrupt Status register bit description Address: Content of the ...
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NXP Semiconductors Table 57. HcInterruptEnable - Host Controller Interrupt Enable register bit allocation Address: Content of the base address register + 10h Bit 31 Symbol MIE OC Reset 0 Access R/W R/W Bit 23 Symbol Reset 0 Access R/W R/W ...
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NXP Semiconductors Table 58. HcInterruptEnable - Host Controller Interrupt Enable register bit description Address: Content of the base address register + 10h Bit Symbol Description 2 SF Start-of-Frame: 0 — Ignore 1 — Enables interrupt generation because of Start-of-Frame. 1 ...
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NXP Semiconductors Table 60. HcInterruptDisable - Host Controller Interrupt Disable register bit description Address: Content of the base address register + 14h Bit Symbol Description 31 MIE Master Interrupt Enable: 0 — Ignore 1 — Disables interrupt generation because of ...
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NXP Semiconductors Table 61. HcHCCA - Host Controller Communication Area register bit allocation Address: Content of the base address register + 18h Bit 31 Symbol Reset 0 Access R/W R/W Bit 23 Symbol Reset 0 Access R/W R/W Bit 15 ...
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NXP Semiconductors Bit 7 Symbol Reset 0 Access R Table 64. HcPeriodCurrentED - Host Controller Period Current Endpoint Descriptor register bit description Address: Content of the base address register + 1Ch Bit Symbol Description PCED[27:0] Period Current ...
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NXP Semiconductors 11.1.10 HcControlCurrentED register The HcControlCurrentED register contains the physical address of the current ED of the control list. The bit allocation is given in Table 67. HcControlCurrentED - Host Controller Control Current Endpoint Descriptor register bit allocation Address: ...
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NXP Semiconductors Bit 23 Symbol Reset 0 Access R/W R/W Bit 15 Symbol Reset 0 Access R/W R/W Bit 7 Symbol Reset 0 Access R/W R/W [1] The reserved bits must always be written with the reset value. Table 70. ...
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NXP Semiconductors Bit 7 Symbol Reset 0 Access R/W R/W [1] The reserved bits must always be written with the reset value. Table 72. HcBulkCurrentED - Host Controller Bulk Current Endpoint Descriptor register bit description Address: Content of the base ...
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NXP Semiconductors Table 74. HcDoneHead - Host Controller Done Head register bit description Address: Content of the base address register + 30h Bit Symbol Description DH[27:0] Done Head: When completed, the Host Controller writes ...
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NXP Semiconductors Table 76. HcFmInterval - Host Controller Frame Interval register bit description Address: Content of the base address register + 34h Bit Symbol Description 31 FIT Frame Interval Toggle: The HCD toggles this bit whenever it loads a new ...
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NXP Semiconductors Table 78. HcFmRemaining - Host Controller Frame Remaining register bit description Address: Content of the base address register + 38h Bit Symbol Description 31 FRT Frame Remaining Toggle: This bit is loaded from FIT (bit 31 of HcFmInterval) ...
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NXP Semiconductors 11.1.17 HcPeriodicStart register This register has a 14-bit programmable value that determines when is the earliest time for the Host Controller to start processing the periodic list. For bit allocation, see Table 81. HcPeriodicStart - Host Controller Periodic ...
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NXP Semiconductors Bit 23 Symbol Reset 0 Access R/W R/W Bit 15 Symbol Reset 0 Access R/W R/W Bit 7 Symbol Reset 0 Access R/W R/W [1] The reserved bits must always be written with the reset value. Table 84. ...
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NXP Semiconductors Bit 7 Symbol Reset 0 Access R [1] The reserved bits must always be written with the reset value. Table 86. HcRhDescriptorA - Host Controller Root Hub Descriptor A register bit description Address: Content of the base address ...
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NXP Semiconductors Table 87. HcRhDescriptorB - Host Controller Root Hub Descriptor B register bit allocation Address: Content of the base address register + 4Ch Bit 31 Symbol Reset 0 Access R/W R/W Bit 23 Symbol Reset 0 Access R/W R/W ...
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NXP Semiconductors Bit 23 Symbol Reset 0 Access R/W R/W Bit 15 Symbol DRWE Reset 0 Access R/W R/W Bit 7 Symbol Reset 0 Access R/W R/W [1] The reserved bits must always be written with the reset value. Table ...
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NXP Semiconductors Table 90. HcRhStatus - Host Controller Root Hub Status register bit description Address: Content of the base address register + 50h Bit Symbol Description reserved - 1 OCI Overcurrent Indicator: This bit reports overcurrent conditions ...
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NXP Semiconductors Table 92. HcRhPortStatus[2:1] - Host Controller Root Hub Port Status[2:1] register bit description Address: Content of the base address register + 54h Bit Symbol Description reserved - 20 PRSC Port Reset Status Change: This bit ...
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NXP Semiconductors Table 92. HcRhPortStatus[2:1] - Host Controller Root Hub Port Status[2:1] register bit description Address: Content of the base address register + 54h Bit Symbol Description 8 PPS On read Port Power Status: This bit reflects the port power ...
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NXP Semiconductors Table 92. HcRhPortStatus[2:1] - Host Controller Root Hub Port Status[2:1] register bit description Address: Content of the base address register + 54h Bit Symbol Description 2 PSS On read Port Suspend Status: This bit indicates whether the port ...
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NXP Semiconductors Bit 23 Symbol Reset 0 Access R Bit 15 Symbol Reset 0 Access R Bit 7 Symbol Reset 0 Access R Table 94. CAPLENGTH/HCIVERSION - Capability Length/Host Controller Interface Version Number register bit description Address: Content of the ...
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NXP Semiconductors Table 96. HCSPARAMS - Host Controller Structural Parameters register bit description Address: Content of the base address register + 04h Bit Symbol Description reserved - N_CC Number of Companion Controller: This field ...
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NXP Semiconductors Bit 7 Symbol Reset 0 Access R Table 98. HCCPARAMS - Host Controller Capability Parameters register bit description Address: Content of the base address register + 08h Bit Symbol Description reserved - ...
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NXP Semiconductors Table 99. USBCMD - USB Command register bit allocation Address: Content of the base address register + 20h Bit 31 Symbol Reset 0 Access R/W R/W Bit 23 Symbol Reset 0 Access R/W R/W Bit 15 Symbol Reset ...
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NXP Semiconductors Table 100. USBCMD - USB Command register bit description Address: Content of the base address register + 20h Bit Symbol Description 6 IAAD Interrupt on Asynchronous Advance Doorbell: This bit is used as a doorbell by software to ...
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NXP Semiconductors Table 101. USBSTS - USB Status register bit allocation Address: Content of the base address register + 24h Bit 31 Symbol Reset 0 Access R/W R/W Bit 23 Symbol Reset 0 Access R/W R/W Bit 15 Symbol ASS ...
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NXP Semiconductors Table 102. USBSTS - USB Status register bit description Address: Content of the base address register + 24h Bit Symbol Description 4 HSE Host System Error: The Host Controller sets this bit when a serious error occurs during ...
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NXP Semiconductors Bit 15 Symbol Reset 0 Access R/W R/W Bit 7 [1] Symbol reserved Reset 0 Access R/W R/W [1] The reserved bits must always be written with the reset value. Table 104. USBINTR - USB Interrupt Enable register ...
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NXP Semiconductors Table 105. FRINDEX - Frame Index register bit allocation Address: Content of the base address register + 2Ch Bit 31 Symbol Reset 0 Access R/W R/W Bit 23 Symbol Reset 0 Access R/W R/W Bit 15 [1] Symbol ...
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NXP Semiconductors system software loads this register before starting the schedule execution by the Host Controller. The memory structure referenced by this physical memory pointer is assumed aligned. The contents of this register are combined with the ...
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NXP Semiconductors Table 110. ASYNCLISTADDR - Current Asynchronous List Address register bit allocation Address: Content of the base address register + 38h Bit 31 Symbol Reset 0 Access R/W R/W Bit 23 Symbol Reset 0 Access R/W R/W Bit 15 ...
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NXP Semiconductors Bit 7 Symbol Reset 0 Access R/W R/W [1] The reserved bits must always be written with the reset value. Table 113. CONFIGFLAG - Configure Flag register bit description Address: Content of the base address register + 60h ...
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NXP Semiconductors Bit 7 Symbol SUSP FPR Reset 0 Access R/W R/W [1] The reserved bits must always be written with the reset value. Table 115. PORTSC Port Status and Control 1, 2 register bit description Address: ...
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NXP Semiconductors Table 115. PORTSC Port Status and Control 1, 2 register bit description Address: Content of the base address register + 64h + (4 Bit Symbol Description LS[1:0] Line Status: This field reflects ...
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NXP Semiconductors Table 115. PORTSC Port Status and Control 1, 2 register bit description Address: Content of the base address register + 64h + (4 Bit Symbol Description 6 FPR Force Port Resume: Logic 1 means resume ...
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NXP Semiconductors Table 116. System Tuning register bit allocation Address: Content of the base address register + 6Ch Bit 31 Symbol Reset 0 Access R/W R/W Bit 23 Symbol Reset 0 Access R/W R/W Bit 15 Symbol Reset 0 Access ...
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NXP Semiconductors Table 118. Ring buffering disable SYS_TUNE pin Table 119. Watermark disable SYS_TUNE pin ISP1564_1 Product data sheet RBD bit WMD bit Rev. 01 — 4 December ...
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NXP Semiconductors 12. Limiting values Table 120. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V IO supply voltage CC(IO) V regulator supply voltage CC(REG) V auxiliary input/output supply CC(IO)AUX voltage V auxiliary supply ...
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NXP Semiconductors 14. Static characteristics Table 122. Static characteristics 3 3 +85 C; unless otherwise specified. CC(IO) amb Typical values are 3 CC(IO) Symbol ...
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NXP Semiconductors Table 125. Static characteristics: USB interface block (pins DM1 to DM2 and DP1 to DP2 3 3 +85 C; unless otherwise specified. CCA(AUX) amb Typical values are at ...
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NXP Semiconductors Table 126. Current consumption CC(IO)AUX CC(AUX 3 3 +85 C; unless otherwise specified. CC(REG) amb Typical values are at V ...
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NXP Semiconductors 15. Dynamic characteristics Table 128. Dynamic characteristics: system clock timing +85 C; unless otherwise specified. CC(IO) amb Typical values are 3 ...
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NXP Semiconductors Table 131. Dynamic characteristics: high-speed source electrical characteristics +85 C; unless otherwise specified. CCA(AUX) amb Typical values are 3 CCA(AUX) Symbol ...
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NXP Semiconductors T PERIOD +3.3 V crossover point differential data lines the bit duration corresponding to the USB data rate. PERIOD Fig 8. USB source differential data-to-EOP transition skew and EOP width 15.1 Timing Table 134. ...
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NXP Semiconductors Fig 9. PCI clock CLK input delay Fig 10. PCI input timing CLK output delay output Fig 11. PCI output timing ISP1564_1 Product data sheet t high 0.6V CC(IO) 0.5V CC(IO) 0.4V CC(IO) 0.3V CC(IO) 0.2V CC(IO) t ...
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NXP Semiconductors 16. Package outline LQFP100: plastic low profile quad flat package; 100 leads; body 1 pin 1 index 100 DIMENSIONS (mm are the original ...
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NXP Semiconductors TFBGA100: plastic thin fine-pitch ball grid array package; 100 balls; body 0.7 mm ball A1 index area ball index ...
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NXP Semiconductors 17. Soldering This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 17.1 Introduction to soldering Soldering ...
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NXP Semiconductors 17.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including ...
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NXP Semiconductors Fig 14. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 18. Abbreviations Table 137. Abbreviations Acronym CMOS DID DWORD ED EEPROM EHCI ...
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NXP Semiconductors Table 137. Abbreviations Acronym PCI-SIG PLL PMC PME POR POST SOF STB TD USB VID 19. References [1] Universal Serial Bus Specification — Rev. 2.0 [2] Enhanced Host Controller Interface Specification for Universal Serial Bus — Rev. 1.0 ...
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NXP Semiconductors 21. Legal information 21.1 Data sheet status [1][2] Document status Product status Objective [short] data sheet Development Preliminary [short] data sheet Qualification Product [short] data sheet Production [1] Please consult the most recently issued document before initiating or ...
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NXP Semiconductors 23. Tables Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .2 Table 2. Pin description . . . . . . . ...
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NXP Semiconductors Command Status register bit description . . . . .39 Table 55. HcInterruptStatus - Host Controller Interrupt Status register bit allocation . . . . . . .40 Table 56. HcInterruptStatus - Host Controller Interrupt Status register bit ...
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NXP Semiconductors description . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Table 101.USBSTS - USB Status register bit allocation . ...
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NXP Semiconductors 24. Figures Fig 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Fig 2. Pin configuration ...
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NXP Semiconductors 25. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . ...
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NXP Semiconductors 11.2.2 HCSPARAMS register . . . . . . . . . . . . . . . . . . 62 11.2.3 HCCPARAMS register . . . . . . . . . . . . . ...