ISP1564HLUM STEricsson, ISP1564HLUM Datasheet - Page 45

• Manufacturer Part Number: ISP1564HLUM
• Manufacturer: STEricsson

Specifications of ISP1564HLUM

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
Table 60.
Address: Content of the base address register + 14h
ISP1564_1
Product data sheet
Bit
31
30
29 to 7
6
5
4
3
2
1
0
Symbol
MIE
OC
reserved
RHSC
FNO
UE
RD
SF
WDH
SO
HcInterruptDisable - Host Controller Interrupt Disable register bit description
11.1.7 HcHCCA register
Description
Master Interrupt Enable:
0 — Ignore
1 — Disables interrupt generation because of events specified in other bits of this register.
This field is set after a hardware or software reset. Interrupts are disabled.
Ownership Change:
0 — Ignore
1 — Disables interrupt generation because of ownership change.
-
Root Hub Status Change:
0 — Ignore
1 — Disables interrupt generation because of root hub status change.
Frame Number Overflow:
0 — Ignore
1 — Disables interrupt generation because of frame number overflow.
Unrecoverable Error:
0 — Ignore
1 — Disables interrupt generation because of unrecoverable error.
Resume Detect:
0 — Ignore
1 — Disables interrupt generation because of resume detect.
Start-of-Frame:
0 — Ignore
1 — Disables interrupt generation because of Start-of-Frame.
HcDoneHead Write-back:
0 — Ignore
1 — Disables interrupt generation because of HcDoneHead write-back.
Scheduling Overrun:
0 — Ignore
1 — Disables interrupt generation because of scheduling overrun.
The HcHCCA register contains the physical address of Host Controller Communication
Area (HCCA). The bit allocation is given in
restrictions by writing all 1s to HcHCCA and reading the content of HcHCCA. The
alignment is evaluated by examining the number of zeroes in lower order bits. The
minimum alignment is 256 bytes; therefore, bits 0 through 7 will always return logic 0
when read. This area is used to hold control structures and the interrupt table that are
accessed by both the Host Controller and the HCD.
Rev. 01 — 4 December 2006
Table
61. The HCD determines alignment
HS USB PCI Host Controller
© NXP B.V. 2006. All rights reserved.
ISP1564
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