IDT77305L15PF IDT, Integrated Device Technology Inc, IDT77305L15PF Datasheet
IDT77305L15PF
Specifications of IDT77305L15PF
Related parts for IDT77305L15PF
IDT77305L15PF Summary of contents
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Four Independent Input 128 x9 FIFO Queues Nine bit wide input FIFOs Single selectable bit output bus "UtopiaRx" or "UtopiaTx" Utopia compliant interface signaling options Separate clocks for input and output Selectable Automatic byte insertion for 8-bit ...
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IDT77305 UtopiaFIFO™ (128 Multiplexer-FIFO The IDT77305 UtopiaFIFO is a high-speed, low power, four to one, muxed FIFO with multiple programmable modes of operation. The IDT77305 can be used as a stand alone device ...
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IDT77305 UtopiaFIFO™ (128 Multiplexer-FIFO Name I/O BDI I Byte Deletion/Insertion. BDI = "1" insert byte 6 or delete byte 5, BDI = "0" no change to bytes (see Table 4). ...
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IDT77305 UtopiaFIFO™ (128 Multiplexer-FIFO Name I/O LDM I/O Load Mux. RRE = "1" and MSE = "1": LDM is an output telling Slave to latch the Mux select address on the next clock ...
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IDT77305 UtopiaFIFO™ (128 Multiplexer-FIFO Symbol V Terminal Voltage with respect to ground TERM T Operating Temperature A T-Bias Temperature under Bias T-STG Storage Temperature I DC Output Current OUT Symbol V Commercial Supply ...
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IDT77305 UtopiaFIFO™ (128 Multiplexer-FIFO RX Mode Symbol t Cell Available Set-up Time, CLAVR to WCLK CLAVS t Cell Available Hold Time, WCLK to CLAVR CLAVH Enable Set-up Time, ENS to RCLK t ENSS ...
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IDT77305 UtopiaFIFO™ (128 Multiplexer-FIFO Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels AC Test Load 50 I Figure 1: AC Test Load 6 5 ...
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IDT77305 UtopiaFIFO™ (128 Multiplexer-FIFO Rx Mode Symbol f Clock Cycle Frequency S t Data Access Time A t Clock Cycle Time CLK t Clock High Time CLKH t Clock Low Time CLKL (1) ...
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IDT77305 UtopiaFIFO™ (128 Multiplexer-FIFO Rx Mode Symbol f Clock Cycle Frequency S t Data Access Time A t Clock Cycle Time CLK t Clock High Time CLKH t Clock Low Time CLKL (1) ...
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IDT77305 UtopiaFIFO™ (128 Multiplexer-FIFO mux select lines provide user control of FIFO selection. SINGLE DEVICE OPERATION The two programmable interface signaling modes of operation are Utopia Receive (UtopiaRx) and Utopia transmit (UtopiaTx). Both ...
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IDT77305 UtopiaFIFO™ (128 Multiplexer-FIFO RST (I) CLAVR (A..D) (O) ENR (A..D) (I) ENS (O) SOCS (O) Q0ÑQ17 (O) LDM (O) LDM (I) OE (I) CR0-CR3, (I/O) CRC, ECT, CSS Commercial and Industrial Temperature ...
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IDT77305 UtopiaFIFO™ (128 Multiplexer-FIFO RST (I) CLAVR (A..D) (I) ENR (A..D) (O) CLAVS (O) ENS (I) SOCS (O) Q0ÑQ17 (O) LDM (O) LDM (I) OE (I) CR0-CR3, (I/O) CRC, ECT, CSS t RS ...
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IDT77305 UtopiaFIFO™ (128 Multiplexer-FIFO The selection process begins one cycle prior to the completion of the current FIFOs cell transfer (as defined by the Cell Size Register). On one cycle, the UtopiaFIFO determines ...
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IDT77305 UtopiaFIFO™ (128 Multiplexer-FIFO the Mux1 and Mux 2 lines. This will latch the address. There must be a cell to transfer in the selected FIFO once LDM is asserted new ...
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IDT77305 UtopiaFIFO™ (128 Multiplexer-FIFO All first Rank UtopiaFIFOs are set as Masters with the second Rank having one Master and one Slave. The master/slave control signal- ing for the Rx mode is shown ...
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IDT77305 UtopiaFIFO™ (128 Multiplexer-FIFO t CLK WCLK (I) t CLKH t CLAVS CLAVR (I) ENR (O) SOCR (I) DATA (I) Figure 3. UtopiaFIFO Rx Mode Input Waveforms t CLK RCLK (I) t CLKH ...
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IDT77305 UtopiaFIFO™ (128 Multiplexer-FIFO RCLK (I) t PCLAV CLAVS (O) t ENSS ENS (I) SOCS ( (O) (2) MUXn (O) (1) MUX (I) FIFO X n (4) LDM (O) ...
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IDT77305 UtopiaFIFO™ (128 Multiplexer-FIFO WCLK (I) t PCLAV CLAVR (O) ENR (I) SOCR ( LB-6 LB-5 LB-4 Data (I) Figure 5b. UtopiaFIFO Tx Mode Input Waveforms (Continuous Cell Transfers) ...
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IDT77305 UtopiaFIFO™ (128 Multiplexer-FIFO 100 XXXX 0001 000 0000 XXX1 100X 011 0000 1000 111 XXXX ...
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IDT77305 UtopiaFIFO™ (128 Multiplexer-FIFO MASTER (B) LDM SLAVE (D) LDM Figure 8. UtopiaRx Output Signaling: Master/Slave Building-Block MASTER (B) LDM SLAVE (D) LDM Figure 9. UtopiaTx Output Signaling: Master/Slave Building-Block NOTES: M — ...
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IDT77305 UtopiaFIFO™ (128 Multiplexer-FIFO 9 36 UtopiaFIFO #1 H UtopiaFIFO #2 H UtopiaFIFO #3 H UtopiaFIFO #4 H Rank 1 Figure 10a. 16 9-bit Channels to One 36-bit Channel Implementation ...
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IDT77305 UtopiaFIFO™ (128 Multiplexer-FIFO RANK 1 UtopiaFIFO #1 CLAVS ENS RANK 1 UtopiaFIFO # SOCS RANK 1 UtopiaFIFO #3 RANK 1 UtopiaFIFO #4 NOTE: 1. Rank 1 devices 1, 3, and ...
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IDT77305 UtopiaFIFO™ (128 Multiplexer-FIFO Commercial and Industrial Temperature Ranges 23 ...
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IDT77305 UtopiaFIFO™ (128 Multiplexer-FIFO RANK 1 UtopiaFIFO #1 CLAVS ENS RANK 1 UtopiaFIFO # SOCS RANK 1 UtopiaFIFO #3 OPEN RANK 1 UtopiaFIFO #4 NOTE: 1. Rank 1 devices 1, 3, ...
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IDT77305 UtopiaFIFO™ (128 Multiplexer-FIFO RANK 2 RCLK (I) ENS (O) CLAVS (I) SOCS ( ( M1, M2 (I,O) LDM (I, O) RANK 2 RCLK (I) ENS (O) CLAVS (I) ...
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IDT77305 UtopiaFIFO™ (128 Multiplexer-FIFO UtopiaFIFO 1 UtopiaFIFO 2 UtopiaFIFO 3 UtopiaFIFO 4 Figure 11. 16 9-bit Channels to One 18-bit Channel Implementation BSS BSS ...
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IDT77305 UtopiaFIFO™ (128 Multiplexer-FIFO IDT NNNNN A Device Type Power 12/1/95: Initial Draft 1/15/95: Corrected Typographical Errors 8/14/95: Added AC specs and correct diagrams and upgraded to "PRELIMINARY" 12/3/96: Changed the definition of ...