GCIXP1240AB 837151 Intel, GCIXP1240AB 837151 Datasheet - Page 126

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GCIXP1240AB 837151

Manufacturer Part Number
GCIXP1240AB 837151
Description
Manufacturer
Intel
Datasheet

Specifications of GCIXP1240AB 837151

Lead Free Status / Rohs Status
Not Compliant
Intel
126
Figure 65. Pipelined SRAM Read Burst of Four From Bank 0 Followed by Write Burst of Four
®
IXP1240 Network Processor
From Bank 8
Note 1: There is always a 1 clock cycle idle state on the data bus when switching from read to write.
SLOW_EN_L
HIGH_EN_L
LOW_EN_L
CE_L[3:0]
DQ[31:0]
MRD_L
SWE_L
FWE_L
SOE_L
A[18:0]
SCLK
CE_L<3:0> = 1110
A0
A1
D(A0) D(A1)
A2
A3
D(A2) D(A3)
(see Note 1)
State
Idle
D(A4) D(A5) D(A6)
A4
CE_L<3:0> = 1110
A5
A6
D(A7)
A7
Datasheet
A8612-01

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