GCIXP1240AB 837151 Intel, GCIXP1240AB 837151 Datasheet - Page 75

• Manufacturer Part Number: GCIXP1240AB 837151
• Manufacturer: Intel

Specifications of GCIXP1240AB 837151

• Lead Free Status / Rohs Status: Not Compliant

4.3.4.3
Datasheet
Table 40. 33 MHz PCI Signal Timing
Table 41. 66 MHz PCI Signal Timing
PCI Bus Signals Timing
1. These parameters are at variance with those in the PCI Local Bus Specification, Revision 2.2.
2. Point-to-point signals are REQ_L, GNT_L.
3. Not tested. Guaranteed by design.
4. Bused signals are AD, CBE_L, PAR, PERR_L, SERR_L, FRAME_L, IRDY_L, TRDY_L, DEVSEL_L, STOP_L
1. These parameters are at variance with those in the PCI Local Bus Specification, Revision 2.2.
2. Point-to-point signals are REQ_L, GNT_L.
3. Not tested. Guaranteed by design.
4. Bused signals are AD, CBE_L, PAR, PERR_L, SERR_L, FRAME_L, IRDY_L, TRDY_L, DEVSEL_L, STOP_L.
T
T
(point-to-point)
T
T
T
T
(point-to-point)
T
T
T
(point-to-point)
T
T
T
T
(point-to-point)
T
on
off
su
su
on
off
su
su
val
val
h
val
val
h
1
1
3
3
3
3
1
1
1
1
Symbol
Symbol
CLK to signal valid delay, bused
signals
CLK to signal valid delay,
point-to-point signals
Float to active delay
Active to float delay
Input setup time to CLK, bused
signals
Input setup time to CLK,
point-to-point signals
Input signal hold time from CLK
CLK to signal valid delay, bused
signals
CLK to signal valid delay,
point-to-point signals
Float to active delay
Active to float delay
Input setup time to CLK, bused
signals
Input setup time to CLK,
point-to-point signals
Input signal hold time from CLK
2
4
Parameter
Parameter
2
4
2
2
1.5
1.5
2
---
7
10
1
1.5
1.5
2
---
3
5
1
Minimum
Minimum
Intel
®
IXP1240 Network Processor
11
12
---
28
---
---
---
7
7
---
6
---
---
---
Maximum
Maximum
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
Unit
75