GWIXP465BAB Intel, GWIXP465BAB Datasheet

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GWIXP465BAB

Manufacturer Part Number
GWIXP465BAB
Description
Manufacturer
Intel
Datasheet

Specifications of GWIXP465BAB

Core Operating Frequency
266MHz
Operating Supply Voltage (typ)
1.3/1.5/2.5/3.3V
Operating Supply Voltage (max)
1.575/2.7/3.465V
Operating Supply Voltage (min)
1.235/2.3/3.135V
Package Type
BGA
Pin Count
544
Mounting
Surface Mount
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Not Compliant
Intel
Line of Network Processors
Product Features
For a complete list of product features, see
describes in full the features of the silicon. Some of these features require enabling software
supplied by Intel. Please refer to the Intel
information on which features are enabled at this time.
These features do not require enabling
software
Typical Applications
Intel XScale
PCI v. 2.2 33/66 MHz (Host/Option)
USB 1.1 Device Controller
USB 2.0 Host Controller
DDRI SDRAM Interface
Master/Target Capable Expansion bus
Two UARTs
Internal Bus Performance Monitoring Unit
16 GPIO
Four Internal Timers
Synchronous Serial Protocol (SSP) Port
I
Spread Spectrum clocking for Reduced
EMI
Packaging
— 544-Pin PBGA
— Commercial/Extended Temperature
— Lead-Free Support
Small-to-Medium Business Router
Industrial Controllers
Modular Router
Access Points (802.11a/b/g)
Network-Attached Storage
Wired/Wireless RFID Readers
2
C Interface
®
IXP45X and Intel
®
Core — Up to 667 MHz
®
“Product Features” on page
IXP400 Software Programmer’s Guide for
These features require enabling software.
For information on which features are
enabled at this time, see the Intel
Software Programmer’s Guide.
Cryptography Unit (Random Number
Generator and Exponentiation Unit)
Encryption/Authentication (AES/
AES-CCM/3DES/DES/SHA-1/SHA-256/
SHA-384/SHA-512/MD-5)
Two High-Speed, Serial Interfaces
Three Network Processor Engines
Up to three MII Interfaces
Up to six SMII Interfaces
Up to one UTOPIA Level 2 Interface
IEEE-1588 Hardware Assist
VoIP Integrated Access Device (IAD)
Video IP Telephones
Security Gateway/Router
Network Printers
Control Plane
Mini-DSLAM
®
IXP46X Product
Document Number:
9. This document
Datasheet
®
IXP400
306261-002
May 2005

GWIXP465BAB Summary of contents

Page 1

... Line of Network Processors Product Features For a complete list of product features, see describes in full the features of the silicon. Some of these features require enabling software supplied by Intel. Please refer to the Intel information on which features are enabled at this time. These features do not require enabling software ® ...

Page 2

... Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. ...

Page 3

... Instruction Cache ................................................................................................... 36 3.2.6 Data Cache ............................................................................................................ 37 3.2.7 Mini-Data Cache .................................................................................................... 37 3.2.8 Fill Buffer and Pend Buffer..................................................................................... 37 3.2.9 Write Buffer ............................................................................................................ 38 3.2.10 Multiply-Accumulate Coprocessor ......................................................................... 38 3.2.11 Performance Monitoring Unit ................................................................................. 39 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet Document Number: 306261-002 Contents May 2005 3 ...

Page 4

... Bus Signal Timings .............................................................................................. 130 5.6.2.1 PCI ....................................................................................................... 130 5.6.2.2 USB 1.1 Interface................................................................................. 131 5.6.2.3 UTOPIA Level 2 ................................................................................... 132 5.6.2.4 MII/SMII................................................................................................ 133 May 2005 Pin Requirements ................................. 116 CCPLL3 CCOSCP CCOSC ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet Document Number: 306261-002 ...

Page 5

... Lead PBGA Package — First of Two Drawings ............................................................ 41 6 544-Pin Lead PBGA Package — Second of Two Drawings....................................................... 42 7 Package Markings: ® ® Intel IXP45X and Intel Extended and Commercial Temperature, Lead-Free / Compliant with Standard for Restriction on the Use of Hazardous Substances (RoHS) ......................................................... 43 8 Package Markings: ® ® Intel IXP45X and Intel Commercial and Extended Temperature, Lead-Based ...

Page 6

... Contents 32 Expansion Bus Synchronous Timing ........................................................................................ 140 33 Intel Multiplexed Mode.............................................................................................................. 141 34 Intel Simplex Mode ................................................................................................................... 142 35 Motorola* Multiplexed Mode ..................................................................................................... 144 36 Motorola* Simplex Mode .......................................................................................................... 146 37 HPI*–8 Mode Write Accesses .................................................................................................. 147 38 HPI*-16 Multiplexed Write Mode .............................................................................................. 150 39 HPI*-16 Multiplexed Read Mode .............................................................................................. 151 40 HPI*-16 Non-Multiplexed Read Mode ...................................................................................... 152 41 HPI*-16 Non-Multiplexed Write Mode ...

Page 7

... DDRI SDRAM Write Timings Values ........................................................................................138 64 DDRI SDRAM Read Timing Values..........................................................................................139 65 Expansion Bus Synchronous Operation Timing Values ...........................................................140 66 Intel Multiplexed Mode Values..................................................................................................141 67 Intel Simplex Mode Values .......................................................................................................143 68 Motorola* Multiplexed Mode Values .........................................................................................144 69 Motorola* Simplex Mode Values...............................................................................................146 70 HPI* Timing Symbol Description...............................................................................................148 71 HPI*– ...

Page 8

... Power Dissipation Values ......................................................................................................... 163 83 Power Dissipation Test Conditions ........................................................................................... 163 Revision History Date May 2005 March 2005 May 2005 8 Revision Added support for Intel Table 1 on page 14, Figure 3 on page and Table 82 on page Section 4.0, “Package Information” on page 002 “Package Markings” ...

Page 9

... IXP45X/IXP46X product line, such as the Intel® IXP460 or Intel® IXP455 network processors. For details on feature support listed by processor, see Some of the features described in this document require software delivered by Intel. Some features may not be enabled with current software releases. The features which require software are identified within this document ...

Page 10

... Unbuffered DDRI SDRAM support only — eight open pages simultaneously maintained — Support for 32 Mbyte, minimum; 1 Gbyte, maximum — User-enabled, single-bit error correction/multi-bit error detection ECC support (ECC not supported on Intel • Expansion interface — Master/Target interface — 25-bit address — ...

Page 11

... Synchronous flash support • Flow through ZBT SRAM burst support • 80-MHz operation load • Supports even/odd-parity generation and checking in all extended modes and in some legacy modes (Intel and Motorola style bus cycles) — Inbound transfer support • Single transfer or burst support • ...

Page 12

... Extended temperature (-40° to 85° C) — Lead Free Support The remaining features described in the product line features list require software in order for these features to be functional. To determine if the feature is enabled, see the Intel IXP400 Software Programmer’s Guide. • Three network processor engines (NPEs) Used to off load typical Layer-2 networking functions such as: — ...

Page 13

... Time master support — Time target support Notes: 1. This feature requires Intel supplied software. To determine if this feature is enabled by a particular software release, see the Intel 2. Although this feature has direct access from the Intel XScale activity of the MII interfaces which requires Intel-supplied software to operate. ...

Page 14

... IEEE1588 Hardware Assistance SSP Commercial Temperature Extended Temperature These features require Intel-supplied software in order to be operational. To determine if the feature is † enabled, see the Intel †† 4-Port SMII is not supported on the IXP455 network processor. May 2005 14 ® IXP46X Product Line of Network Processors Features ® ...

Page 15

... Intel StrongARM processors are designed with Intel, 0.18-micron semiconductor process technology. This process technology — along with the compactness of the Intel simultaneously process data with up to three integrated network processing engines (NPEs), and numerous dedicated-function peripheral interfaces — enables the IXP45X/IXP46X network processors to operate over a wide range of low-cost networking applications with industry-leading performance ...

Page 16

... Supported 8/16/32 bit + Parity 32 bit at 33/66 MHz Master on North AHB Bus Arbiters AHB Slave / APB Master ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet DDRI Memory Controller Unit 32 Bit + ECC ® Intel XScale Core 32-Kbyte I-Cache 32-Kbyte D-Cache ...

Page 17

... Controller V2.0 Controller High Speed is not PMU Timers Slave Only Master on South AHB ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet Document Number: 306261-002 NPE B North AHB 133MHz x 32 bits NPE C North AHB Arbiter Public Key Exchange Crypto ...

Page 18

... Supported 8/16/32 bit + Parity 32 bit at 33/66 MHz Master on North AHB Bus Arbiters AHB Slave / APB Master ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet DDRI Memory Controller Unit 32 Bit with no ECC ® Intel XScale Core 32-Kbyte I-Cache ...

Page 19

... The network processor engines (NPEs) are dedicated-function processors containing hardware coprocessors integrated into the IXP45X/IXP46X network processors. The NPEs are used to off load processing function required by the Intel XScale core. These NPEs are high-performance, hardware-multi-threaded processors with additional local- hardware-assist functionality used to off load highly processor-intensive functions such as MII (MAC), CRC checking/generation, AAL 2 segmentation and re-assembly, AES, AES-CCM, DES, DES3, SHA-1/256/384/512, MD5, etc ...

Page 20

... The combined forces of the hardware multi-threading, local-code store, independent instruction memory, independent data memory, and parallel processing — contained on the NPE — allows the Intel XScale core to be utilized for application purposes. The multi-processing capability of the peripheral interface functions allows unparalleled performance to be achieved by the application running on the Intel XScale core ...

Page 21

... The South AHB is a 133.32-MHz (which OSC_IN input pin), 32-bit bus that can be mastered by the Intel XScale core, PCI controller, Expansion Bus Interface, USB Host Controller, and the AHB/AHB bridge. The targets of the South AHB Bus can be the DDRI SDRAM, PCI Controller, Queue Manager, Expansion Bus, or the AHB/APB bridge ...

Page 22

... This implementation promotes fairness within the system. 3.1.2.3 Memory Port Interface The Memory Port Interface (MPI 128-bit bus that provides the Intel XScale core a dedicated interface to the DDRI SDRAM. The Memory Port Interface operates at 133.32 MHz (which OSC_IN input pin). ...

Page 23

... The independent NPEs and MACs allow parallel processing of data traffic on the MII interfaces and off loading of processing required by the Intel XScale core. The IXP45X/IXP46X network processors are compliant with the IEEE 802.3 specification. In addition to the MII interfaces, the IXP45X/IXP46X network processors include a single management data interface that is used to configure and control PHY devices that are connected to the MII interfaces ...

Page 24

... DDRI SDRAM technology support • Only unbuffered DRAM support (No registered DRAM support) • Dedicated port for Intel XScale core to DDR SDRAM • Between 32 Mbyte and 1 Gbyte of 32-bit DDR SDRAM for low-cost solutions • Single-bit error correction, multi-bit detection support (ECC) • ...

Page 25

... Mbit 16M x 16 NOTES: 1. Table indicates 32-bit-wide memory subsystem sizes 2. Table indicates 32-bit-wide memory page sizes ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet Document Number: 306261-002 Address Size Leaf Select # Banks Row Col ...

Page 26

... IXP45X/IXP46X network processors. If ECC is required, additional memories would need to be added. For more information on DDRI SDRAM support and configuration see the Intel IXP46X Product Line of Network Processors Developer’s Manual. The memory controller internally interfaces to the North AHB, South AHB, and Memory Port Interface with independent interfaces ...

Page 27

... IXP45X/IXP46X network processors to connect to a wide variety of peripheral devices with varying speeds. The expansion interface supports Intel or Motorola* microprocessor-style bus cycles. The bus cycles can be configured to be multiplexed address/data cycles or separate address/data cycles for each of the eight chip-selects. ...

Page 28

... IXP45X/IXP46X network processors. The high-speed, serial interfaces are capable of supporting various protocols, based on the implementation of the code developed for the network processor engine core. For a list of supported protocols, see the Intel 3.1.11 UARTs The UART interfaces are a 16550-compliant UART with the exception of transmit and receive buffers ...

Page 29

... Internal Bus Performance Monitoring Unit (IBPMU) The IXP45X/IXP46X network processors contain a performance monitoring unit that may be used to capture predefined events within the system outside of the Intel XScale core. These features aid in measuring and monitoring various system parameters that contribute to the overall performance of the processor ...

Page 30

... The IEEE 1588 standard defines several messages that can be used to exchange timing information. The IXP45X/IXP46X network processors implement the IEEE 1588 hardware-assist logic on three of the MII interfaces. Using the hardware assist logic along with software running on the Intel XScale core, a full source or sink capable IEEE-1588 compliant network node can be implemented. ...

Page 31

... Random Number Generator (RNG) • Secure Hash Algorithm (SHA function for the RNG) ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet Document Number: 306261-002 bus. The I C bus is a two-pin serial bus. SDA is the data pin 2 C bus via a buffered interface ...

Page 32

... Additionally status flags are maintained for each queue. The Queue Manager interfaces include an Advanced High-performance Bus (AHB) interface to the NPEs and Intel XScale core (or any other AHB bus master), a Flag Bus interface, an event bus (to the NPE condition select logic), and two interrupts to the Intel XScale core. ...

Page 33

... Performance monitoring unit (PMU) furnishing two 32-bit event counters and one 32-bit cycle counter for analysis of hit rates, etc. This PMU is for the Intel XScale core only. An additional PMU is supplied for monitoring of internal bus performance. • JTAG debug unit that uses hardware break points and 256-entry trace history buffer (for flow- change messages) to debug programs ® ...

Page 34

... Interrupt Request Instruction Cache Instruction 32 Kb Execution Core Data Cache Data 32 Kb Address Mini-Data Cache Data 2 Kb System Debug/ Management PMU JTAG ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet South AHB Bus A9568-01 Document Number: 306261-002 ...

Page 35

... ITLB. The descriptor contains information for logical-to-physical address translation, memory-access permissions, memory-domain identifications, and attributes governing operation of the I-cache. ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet Document Number: 306261-002 • • ...

Page 36

... I-cache, but only when its data operands do not depend on the execution results of the instruction being fetched via the queue. May 2005 36 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet Document Number: 306261-002 ...

Page 37

... Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet Document Number: 306261-002 Functional Overview May 2005 ...

Page 38

... LSBs are added to the 40-bit accumulator. The versions of the multiply-accumulate instructions complete in a single cycle. May 2005 38 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet Document Number: 306261-002 ...

Page 39

... The debug unit — when used with debugger application code running on a host system outside of the Intel XScale core — allows a program, running on the Intel XScale core debugged. It allows the debugger application code or a debug exception to stop program execution and redirect execution to a debug-handling routine ...

Page 40

... Package Drawings The package is shown in May 2005 40 which includes “Package Drawings”, Figure 5 and Figure 6. ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet “Package Markings”, and “Part Document Number: 306261-002 ...

Page 41

... Figure 5. 544-Pin Lead PBGA Package — First of Two Drawings ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet Document Number: 306261-002 Package Information 1.27 0.61 0.75 1.17 Revision 002 May 2005 41 ...

Page 42

... Package Information Figure 6. 544-Pin Lead PBGA Package — Second of Two Drawings May 2005 42 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet Revision 002 Document Number: 306261-002 ...

Page 43

... IXP45X and Intel Extended and Commercial Temperature, Lead-Free / Compliant with Standard for Restriction on the Use of Hazardous Substances (RoHS) i Pin # 1 Notes: 1. Part Number field — For the different part numbers of Intel see Section 4.1.3. ® 2. Package ball counts — Intel IXP45X and Intel 3. Drawing is not to scale. Marking content is an example. ® ...

Page 44

... Intel IXP45X and Intel Commercial and Extended Temperature, Lead-Based i Pin # 1 Notes: 1. Part Number field — For the different part numbers of Intel see Section 4.1.3. ® 2. Package ball counts — Intel IXP45X and Intel 3. Drawing is not to scale. Marking content is an example. ...

Page 45

... IXP460 IXP460 ® Table 8. Intel IXP45X Product Line Part Numbers: Lead (pb) Packaging (Sheet Device IXP455 IXP455 IXP455 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet Document Number: 306261-002 Speed Stepping Part Number (MHz) A0 266 GWIXP460AB A0 667 GWIXP465AET ...

Page 46

... EWIXP455ADT A0 400 EWIXP455ACT A0 266 EWIXP455ABT 14. field in the other tables in this section of the Type Description ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet Temperature Offering Extended Extended Extended Temperature Offering Commercial Commercial Commercial Extended Extended Extended Document Number: ...

Page 47

... Table 23, “GPIO Interface” on page 85 • Table 24, “JTAG Interface” on page 86 • Table 25, “System Interface” on page 86 • Table 26, “Power Interface” on page 88 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet Document Number: 306261-002 Description Package Information May 2005 47 ...

Page 48

... Z VO DDRI_DQ[31: DDRI_CB[7: DDRI_DQS[4: NOTE: This table discusses all features supported on the Intel processor, see Table 1 on page 14. † For a legend of the Type codes, see Table 10 on page May 2005 48 Normal After † Type Software Enables DDR SDRAM Clock Out — Provide the positive differential clocks to the external SDRAM ...

Page 49

... Tied off to DDRI_RCOMP resistor resistor resistor VCCM/ DDRI_VREF VCCM/2 VCCM/2 2 NOTE: This table discusses all features supported on the Intel processor, see Table 1 on page 14. † For a legend of the Type codes, see Table 10 on page May 2005 49 Normal After † Type Software Enables Clock enables — ...

Page 50

... Z VB PCI_CBE_N[3: PCI_PAR PCI_FRAME_N NOTE: This table discusses all features supported on the Intel processor, see Table 1 on page 14. † For a legend of the Type codes, see Table 10 on page May 2005 50 Normal After † Type Software Enables PCI Address/Data bus used to transfer address and bidirectional data to and from multiple PCI devices ...

Page 51

... Z VB PCI_IRDY_N PCI_STOP_N PCI_PERR_N NOTE: This table discusses all features supported on the Intel processor, see Table 1 on page 14. † For a legend of the Type codes, see Table 10 on page May 2005 51 Normal After † Type Software Enables PCI Target Ready informs that the target of the PCI bus is ready to complete the current data phase of a given transaction ...

Page 52

... Z VB PCI_DEVSEL_N PCI_IDSEL PCI_REQ_N[3: NOTE: This table discusses all features supported on the Intel processor, see Table 1 on page 14. † For a legend of the Type codes, see Table 10 on page May 2005 52 Normal After † Type Software Enables PCI System Error asserted when a parity error occurs on special cycles or any other error that will cause the PCI bus not to function properly ...

Page 53

... Reset Software Enables PCI_REQ_N[ PCI_GNT_N[3: PCI_GNT_N[ NOTE: This table discusses all features supported on the Intel processor, see Table 1 on page 14. † For a legend of the Type codes, see Table 10 on page May 2005 53 Normal After † Type Software Enables PCI arbitration request: • ...

Page 54

... Reset Until † Reset Software Enables PCI_INTA_N PCI_CLKIN NOTE: This table discusses all features supported on the Intel processor, see Table 1 on page 14. † For a legend of the Type codes, see Table 10 on page May 2005 54 Normal After † Type Software Enables PCI interrupt: Used to request an interrupt. ...

Page 55

... V VOD OD HSS soft fuse (refer to Expansion Bus Controller chapter of the Intel Product Line of Network Processors Developer’s Manual) and is not being used in a system design, this interface/signal is not required for any connection. ...

Page 56

... Reset Until † Reset Software Enables HSS_RXDATA0 HSS_RXCLK0 NOTE: This table discusses all features supported on the Intel processor, see Table 1 on page 14. † For a legend of the Type codes, see Table 10 on page May 2005 56 Normal After † Type Software Enables Receive data input. Can be sampled on the rising or falling edge of the receive clock. ...

Page 57

... V VOD OD HSS soft fuse (refer to Expansion Bus Controller chapter of the Intel Product Line of Network Processors Developer’s Manual) and is not being used in a system design, this interface/signal is not required for any connection. ...

Page 58

... Reset Until † Reset Software Enables HSS_RXDATA1 HSS_RXCLK1 NOTE: This table discusses all features supported on the Intel see Table 1 on page 14. † For a legend of the Type codes, see Table 10 on page May 2005 58 Normal After † Type Software Enables Receive data input. Can be sampled on the rising or falling edge of the receive clock. ...

Page 59

... Z NOTE: This table discusses all features supported on the Intel see Table 1 on page 14. † For a legend of the Type codes, see Table 10 on page †† For information on selecting the desired interface, see the Intel May 2005 59 Normal After † Type Software ...

Page 60

... Z NOTE: This table discusses all features supported on the Intel see Table 1 on page 14. † For a legend of the Type codes, see Table 10 on page †† For information on selecting the desired interface, see the Intel May 2005 60 Normal After † Type Software ...

Page 61

... VO O signal should be pulled high with a 10-KΩ resistor. When this interface is disabled via the UTOPIA and/or the NPE-A Ethernet soft fuse (refer to Expansion Bus Controller chapter of the Intel ® IXP46X Product Line of Network Processors Developer’s Manual) and is not IXP45X and Intel being used in a system design, this interface/signal is not required for any connection ...

Page 62

... When this interface/signal is enabled and is not being used in a system design, the interface/ signal should be pulled high with a 10-KΩ resistor. When this interface is disabled via the UTOPIA and/or the NPE-A Ethernet soft fuse (refer to Expansion Bus Controller chapter of the Intel ® ...

Page 63

... VI I signal should be pulled high with a 10-KΩ resistor. When this interface is disabled via the UTOPIA and/or the NPE-A Ethernet soft fuse (refer to Expansion Bus Controller chapter of the Intel ® IXP46X Product Line of Network Processors Developer’s Manual) and is not IXP45X and Intel being used in a system design, this interface/signal is not required for any connection ...

Page 64

... When this interface/signal is enabled and is not being used in a system design, the interface/ signal should be pulled high with a 10-KΩ resistor. When this interface is disabled via the UTOPIA and/or the NPE-A Ethernet soft fuse (refer to Expansion Bus Controller chapter of the Intel ® ...

Page 65

... ETHA_COL NOTE: This table discusses all features supported on the Intel see Table 1 on page 14. † For a legend of the Type codes, see Table 10 on page †† For information on selecting the desired interface, see the Intel May 2005 65 Normal After † Type ...

Page 66

... When this interface/signal is enabled and is not being used in a system design, the interface/ signal should be pulled high with a 10-KΩ resistor. When this interface is disabled via the UTOPIA and/or the NPE-A Ethernet soft fuse (refer to Expansion Bus Controller chapter of the Intel ® ...

Page 67

... Z NOTE: This table discusses all features supported on the Intel see Table 1 on page 14. † For a legend of the Type codes, see Table 10 on page †† For information on selecting the desired interface, see the Intel May 2005 67 Normal After † Type Software Enables Receive PHY address bus ...

Page 68

... SMII_CLK ETHB_TXDATA[3:0] / SMII_TXDATA[ SMII_TXDATA[1] / SMII_TXDATA[2] / SMII_TXDATA[3] NOTE: This table discusses all features supported on the Intel see Table 1 on page 14. † For a legend of the Type codes, see Table 10 on page †† Please refer to Intel ® ® IXP46X Product Line of Network Processors Developer’s Manual for information on how to select the interface desired ...

Page 69

... SMII_TXCLK ETHB_RXCLK / SMII_RXCLK NOTE: This table discusses all features supported on the Intel see Table 1 on page 14. † For a legend of the Type codes, see Table 10 on page †† Please refer to Intel ® ® IXP46X Product Line of Network Processors Developer’s Manual for information on how to select the interface desired ...

Page 70

... Enables ETHB_RXDATA[3:0] / SMII_RXDATA[ SMII_RXDATA[1] / SMII_RXDATA[2] / SMII_RXDATA[3] NOTE: This table discusses all features supported on the Intel see Table 1 on page 14. † For a legend of the Type codes, see Table 10 on page ® ® †† Please refer to Intel IXP46X Product Line of Network Processors Developer’s Manual for information on how to select the interface desired ...

Page 71

... ETHB_RXDV / SMII_RXSYNC ETHB_COL NOTE: This table discusses all features supported on the Intel see Table 1 on page 14. † For a legend of the Type codes, see Table 10 on page †† Please refer to Intel ® ® IXP46X Product Line of Network Processors Developer’s Manual for information on how to select the interface desired ...

Page 72

... Management data clock. Management data interface clock is used to clock the MDIO signal as an output and sample the MDIO as an input. The ETH_MDC is an input on power up and can I/O configured output through an Intel API as documented in the Intel Programmer’s Guide. ® ® ...

Page 73

... ETHC_TXDATA[ SMII_TXDATA[5] ETHC_TXEN NOTE: This table discusses all features supported on the Intel see Table 1 on page 14. † For a legend of the Type codes, see Table 10 on page †† Please refer to Intel ® ® IXP46X Product Line of Network Processors Developer’s Manual for information on how to select the interface desired ...

Page 74

... ETHC_RXDATA[ SMII_RXDATA[5] ETHC_RXDV NOTE: This table discusses all features supported on the Intel see Table 1 on page 14. † For a legend of the Type codes, see Table 10 on page †† Please refer to Intel ® ® IXP46X Product Line of Network Processors Developer’s Manual for information on how to select the interface desired ...

Page 75

... Enables ETHC_COL ETHC_CRS NOTE: This table discusses all features supported on the Intel see Table 1 on page 14. † For a legend of the Type codes, see Table 10 on page ® ® †† Please refer to Intel IXP46X Product Line of Network Processors Developer’s Manual for information on how to select the interface desired ...

Page 76

... Very Important Note: See Intel Processors Developer’s Manual for additional details on address strapping. Expansion bus write enable signal is used as an Intel-mode write strobe / Motorola-mode data strobe (EXP_MOT_DS_N) / TI*-mode data strobe (TI_HDS1_N) / ZBT SRAM mode read/ write_n(ZBT_RD_WR_N) for outbound transactions. This signal is an output for outbound transactions ...

Page 77

... Software Enables Used to drive chip selects for outbound transactions for the expansion bus. • Chip selects 0 through 7 can be configured to support Intel/Intel Synchronous/Motorola/ZBT SRAM bus cycles. • Chip selects 4 through 7 can be configured to support TI HPI bus cycles. • These signal are also sampled by the arbiter to determine when to arbitrate. Driving the signals ...

Page 78

... EX_REQ_GNT_N EX_GNT_N[3:1] Z b’111 VO EX_GNT_REQ_N EX_SLAVE_CS_N NOTE: This table discusses all features supported on the Intel processor, see Table 1 on page 14. † For a legend of the Type codes, see Table 10 on page May 2005 78 Normal After † Type Software Enables VB I/O Byte wide parity protection on the EX_DATA[31:0] Signals used by external masters to gain access to the bus ...

Page 79

... Until † Reset Software Enables EX_BURST EX_WAIT_N NOTE: This table discusses all features supported on the Intel processor, see Table 1 on page 14. † For a legend of the Type codes, see Table 10 on page Table 18. UART Interfaces (Sheet Normal After Power Reset † Name ...

Page 80

... VI VI TXDATA1 CTS1_N H VI/H VI/H RTS1_N NOTE: This table discusses all features supported on the Intel processor, see Table 1 on page 14. † For a legend of the Type codes, see Table 10 on page May 2005 80 Normal After † Type Software Enables UART CLEAR-TO-SEND input to UART Pins. ...

Page 81

... VO SSP_TXD SSP_RXD SSP_EXTCLK NOTE: This table discusses all features supported on the Intel processor, see Table 1 on page 14. † For a legend of the Type codes, see Table 10 on page May 2005 81 Normal After † Type Software Enables SSP_SCLK is the serial bit clock used to control the timing of a transfer. SSP_SCLK can be ...

Page 82

... Software Enables Enables I2C_SDA Z Z VOD I2C_SCL Z Z VOD NOTE: This table discusses all features supported on the Intel processor, see Table 1 on page 14. † For a legend of the Type codes, see Table 10 on page May 2005 82 After † Type The receive and transmit data/address line used to communicate between various master and slave I ...

Page 83

... VB USB_DNEG USB_HPOS NOTE: This table discusses all features supported on the Intel see Table 1 on page 14. † For a legend of the Type codes, see Table 10 on page †† Please refer to the Intel ® ® IXP46X Product Line of Network Processors Hardware Design Guidelines for additional board design details. ...

Page 84

... Software † Reset Software Enables Enables OSC_IN n OSC_OUT n NOTE: This table discusses all features supported on the Intel see Table 1 on page 14. † For a legend of the Type codes, see Table 10 on page May 2005 84 Normal After † Type Software Enables Negative signal of the differential USB receiver/driver for the USB host interface. ...

Page 85

... VI GPIO[14 clkout / GPIO[15 NOTE: This table discusses all features supported on the Intel processor, see Table 1 on page 14. † For a legend of the Type codes, see Table 10 on page May 2005 85 † Type General purpose Input/Output pins. May be configured as an input or an output input, each signal may be configured a processor interrupt ...

Page 86

... JTG_TDI VI/H JTG_TDO Z VO JTG_TRST_N H VI/H VI JTG_TCK NOTE: This table discusses all features supported on the Intel see Table 1 on page 14. † For a legend of the Type codes, see Table 10 on page Table 25. System Interface (Sheet Normal After Power Reset † Name on Reset Until † ...

Page 87

... SPARE1 n/a n/a n/a SPARE2 n/a n/a n/a NOTE: This table discusses all features supported on the Intel see Table 1 on page 14. † For a legend of the Type codes, see Table 10 on page May 2005 87 Normal After † Type Software Enables Used as a reset input to the device after power up conditions have been met ...

Page 88

... N/A N/A N/A VCCPLL2 N/A N/A N/A VCCPLL3 N/A N/A N/A NOTE: This table discusses all features supported on the Intel processor, see Table 1 on page 14. † For a legend of the Type codes, see Table 10 on page May 2005 88 Normal After † Type ...

Page 89

... When designing with a multifunction processor, sometimes a board design may be built to allow a group of products to be produced from a single board design. When this occurs, some features of a given processor may not be used. The Intel Processors Hardware Design Guidelines gives the system designer a guide to determine how the signals must be conditioned and how the part behaves under given configurations ...

Page 90

... NOTE: Configuration 1,2 and 3 are set by the Expansion bus configuration when Reset is deasserted. Blank field indicates no physical ball on package. May 2005 90 ® Configuration 3 Intel IXP465 46. ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet Processor Number ® ® Intel IXP460 Intel IXP455 ...

Page 91

... Section 4.2, “Functional Signal Definitions” on page NOTE: Configuration 1,2 and 3 are set by the Expansion bus configuration when Reset is deasserted. Blank field indicates no physical ball on package. ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet Document Number: 306261-002 Processor Number ® ...

Page 92

... NOTE: Configuration 1,2 and 3 are set by the Expansion bus configuration when Reset is deasserted. Blank field indicates no physical ball on package. May 2005 92 ® Configuration 3 Intel IXP465 46. ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet Processor Number ® ® Intel IXP460 Intel IXP455 ...

Page 93

... Section 4.2, “Functional Signal Definitions” on page NOTE: Configuration 1,2 and 3 are set by the Expansion bus configuration when Reset is deasserted. Blank field indicates no physical ball on package. ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet Document Number: 306261-002 Processor Number ® ...

Page 94

... NOTE: Configuration 1,2 and 3 are set by the Expansion bus configuration when Reset is deasserted. Blank field indicates no physical ball on package. May 2005 94 ® Configuration 3 Intel IXP465 46. ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet Processor Number ® ® Intel IXP460 Intel IXP455 ...

Page 95

... Section 4.2, “Functional Signal Definitions” on page NOTE: Configuration 1,2 and 3 are set by the Expansion bus configuration when Reset is deasserted. Blank field indicates no physical ball on package. ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet Document Number: 306261-002 Processor Number ® ...

Page 96

... NOTE: Configuration 1,2 and 3 are set by the Expansion bus configuration when Reset is deasserted. Blank field indicates no physical ball on package. May 2005 96 ® Configuration 3 Intel IXP465 46. ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet Processor Number ® ® Intel IXP460 Intel IXP455 ...

Page 97

... Section 4.2, “Functional Signal Definitions” on page NOTE: Configuration 1,2 and 3 are set by the Expansion bus configuration when Reset is deasserted. Blank field indicates no physical ball on package. ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet Document Number: 306261-002 Processor Number ® ...

Page 98

... NOTE: Configuration 1,2 and 3 are set by the Expansion bus configuration when Reset is deasserted. Blank field indicates no physical ball on package. May 2005 98 ® Configuration 3 Intel IXP465 46. ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet Processor Number ® ® Intel IXP460 Intel IXP455 ...

Page 99

... Section 4.2, “Functional Signal Definitions” on page NOTE: Configuration 1,2 and 3 are set by the Expansion bus configuration when Reset is deasserted. Blank field indicates no physical ball on package. ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet Document Number: 306261-002 Processor Number ® ...

Page 100

... NOTE: Configuration 1,2 and 3 are set by the Expansion bus configuration when Reset is deasserted. Blank field indicates no physical ball on package. May 2005 100 ® Configuration 3 Intel IXP465 46. ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet Processor Number ® ® Intel IXP460 Intel IXP455 ...

Page 101

... Section 4.2, “Functional Signal Definitions” on page NOTE: Configuration 1,2 and 3 are set by the Expansion bus configuration when Reset is deasserted. Blank field indicates no physical ball on package. ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet Document Number: 306261-002 Processor Number ® ...

Page 102

... NOTE: Configuration 1,2 and 3 are set by the Expansion bus configuration when Reset is deasserted. Blank field indicates no physical ball on package. May 2005 102 ® Configuration 3 Intel IXP465 46. ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet Processor Number ® ® Intel IXP460 Intel IXP455 ...

Page 103

... Section 4.2, “Functional Signal Definitions” on page NOTE: Configuration 1,2 and 3 are set by the Expansion bus configuration when Reset is deasserted. Blank field indicates no physical ball on package. ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet Document Number: 306261-002 Processor Number ® ...

Page 104

... NOTE: Configuration 1,2 and 3 are set by the Expansion bus configuration when Reset is deasserted. Blank field indicates no physical ball on package. May 2005 104 ® Configuration 3 Intel IXP465 46. ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet Processor Number ® ® Intel IXP460 Intel IXP455 ...

Page 105

... Section 4.2, “Functional Signal Definitions” on page NOTE: Configuration 1,2 and 3 are set by the Expansion bus configuration when Reset is deasserted. Blank field indicates no physical ball on package. ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet Document Number: 306261-002 Processor Number ® ...

Page 106

... NOTE: Configuration 1,2 and 3 are set by the Expansion bus configuration when Reset is deasserted. Blank field indicates no physical ball on package. May 2005 106 ® Configuration 3 Intel IXP465 46. ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet Processor Number ® ® Intel IXP460 Intel IXP455 ...

Page 107

... Section 4.2, “Functional Signal Definitions” on page NOTE: Configuration 1,2 and 3 are set by the Expansion bus configuration when Reset is deasserted. Blank field indicates no physical ball on package. ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet Document Number: 306261-002 Processor Number ® ...

Page 108

... Blank field indicates no physical ball on package. May 2005 108 ® Configuration 3 Intel IXP465 46. ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet Processor Number ® ® Intel IXP460 Intel IXP455 Config. 1 only Config. 1 only Config. 1 only Config. 1 only X X ...

Page 109

... Section 4.2, “Functional Signal Definitions” on page NOTE: Configuration 1,2 and 3 are set by the Expansion bus configuration when Reset is deasserted. Blank field indicates no physical ball on package. ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet Document Number: 306261-002 Processor Number ® ...

Page 110

... Blank field indicates no physical ball on package. May 2005 110 ® Configuration 3 Intel IXP465 46. ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet Processor Number ® ® Intel IXP460 Intel IXP455 Config. 1 only Config. 1 only Config. 1 only Config. 1 only ...

Page 111

... Section 4.2, “Functional Signal Definitions” on page NOTE: Configuration 1,2 and 3 are set by the Expansion bus configuration when Reset is deasserted. Blank field indicates no physical ball on package. ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet Document Number: 306261-002 Processor Number ® ...

Page 112

... NOTE: Configuration 1,2 and 3 are set by the Expansion bus configuration when Reset is deasserted. Blank field indicates no physical ball on package. May 2005 112 ® Configuration 3 Intel IXP465 46. ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet Processor Number ® ® Intel IXP460 Intel IXP455 ...

Page 113

... Section 4.2, “Functional Signal Definitions” on page NOTE: Configuration 1,2 and 3 are set by the Expansion bus configuration when Reset is deasserted. Blank field indicates no physical ball on package. ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet Document Number: 306261-002 Processor Number ® ...

Page 114

... T max = T - (Ψ case jmax May 2005 114 ® Configuration 3 Intel 46. Table 28 and Table 29 x Power) JT ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet Processor Number ® ® IXP465 Intel IXP460 Intel IXP455 ...

Page 115

... Operation beyond the “operating conditions” is not recommended and extended exposure beyond the “operating conditions” may affect device reliability. ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet Document Number: 306261-002 max, thermal enhancements such as heat sinks or forced air case is the package junction-to-air thermal resistance ...

Page 116

... CCPLL1 , CCPLL2 , CCPLL3 pin and the associated V CCPLL1 pin and the associated V CCPLL2 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet Pin CCOSC CCOSCP , pin of the CCPLL1 supply pin. Both capacitors SS pin ® pin of the CCPLL2 supply pin ...

Page 117

... In order to achieve a 200-nF capacitance, a parallel combination of two 100-nF capacitors may be used as long as the capacitors are placed directly beside each other. V pins, AD10 and AF10. Ensure that both pins are connected as shown in ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet Document Number: 306261-002 ...

Page 118

... Figure 13. V Power Filtering Diagram CCOSC May 2005 118 CCOSC ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet ® pins of the CCOSC supply pin. Both capacitors SSOSC pin and the associated V pin. SSOSC ® Document Number: 306261-002 ...

Page 119

... RCOMP Pin External Resistor Requirements 5.4 DDRI_RCOMP Pin Requirements Figure 15 shows the requirements for the DDRI_RCOMP pin. Figure 15. DDRI_RCOMP Pin External Resistor Requirements ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet Document Number: 306261-002 RCOMP 34 Ω DDR1_RCOMP 20 Ω ...

Page 120

... Input leakage currents include hi-Z output leakage for all bidirectional buffers with tri-state outputs. 2. These values are typical values seen by the manufacturing process and are not tested. 3. For additional information, see the PCI Local Bus Specification, Revision 2.2. 4. Please consult the Intel specification. May 2005 ...

Page 121

... Input leakage currents include hi-Z output leakage for all bidirectional buffers with tri-state outputs. 2. These values are typical values seen by the manufacturing process and are not tested. ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet Document Number: 306261-002 Electrical Specifications Conditions Min ...

Page 122

... OUT OUT 0 < V < V -10 IN CCP Conditions Min. 0.49*V CCM V + DDRI_VREF 0.15 -0 -15mA 1.95 OUT ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet Typ. Max. Units Notes µ Max. Units Notes V 0 0.4 ...

Page 123

... This drive strength setting should be used to avoid ringing when maximum loading or frequency is utilized. Please use IBIS models and simulation tools to guarantee the design. ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet Document Number: 306261-002 Conditions Min ...

Page 124

... OUT 0 < V < V -10 IN CCP Conditions Min. 2 4mA 2.4 OUT I = 4mA OUT 0 < V < V -10 IN CCP ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet Typ. Max. Units Notes µ Typ. Max. Units Notes V 0 0.4 ...

Page 125

... These values are typical values seen by the manufacturing process and are not tested. 2. Voltage output high for this interface is not applicable due to it being an open drain I/O. ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet Document Number: 306261-002 Electrical Specifications Conditions Min ...

Page 126

... V < CCP Conditions Min. 2 2.4 OUT OUT 0 < V < V -10 IN CCP Conditions Min. 2.0 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet Min. Typ. Max. Units Notes 2.0 V 0.8 V 2.4 V 0.4 V 2.4 V 0.4 V -10 10 µ Typ. ...

Page 127

... V/nS to ensure proper PLL operation. To properly guarantee PLL operation at the slower slew rate, the Vih and Vil levels need to be met at the 33.33MHz frequency. ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet Document Number: 306261-002 Conditions Min ...

Page 128

... MHz. Characterized and guaranteed by design, but not 50 KHz tested In te l® MHZ Parameter Min. Max ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet Notes 66 MHZ Units Notes Min. Max 1.5 4 V/ns Document Number: 306261-002 ...

Page 129

... Clock period for expansion bus clock period T Duty cycle for expansion bus clock duty Rise and fall time requirements for T rise/fall expansion bus clock ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet Document Number: 306261-002 Parameter Min. 35 Parameter Min. 40 Parameter Min. ...

Page 130

... PCI Output Timing CLK Output Delay NOTE 0 Figure 18. PCI Input Timing CLK Input May 2005 130 T clk2out(b) and V = 0.2 V LOW CC. T setup(b) Inputs Valid ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet low A9572-01 T hold A9573-01 Document Number: 306261-002 ...

Page 131

... The IXP45X/IXP46X network processors USB 1.1 device interface cannot be line- powered. To assure proper operation with the IXP45X/IXP46X network processors USB interfaces, please ® consult the Intel IXP45X and Intel Design Guidelines and the Intel Update . ® ® Intel IXP45X and Intel ...

Page 132

... UTP_IP_DATA[7:0], UTP_IP_SOC, and UTP_IP_FCI, and UTP_OP_FCI. Figure 20. UTOPIA Level 2 Output Timings Clock Signals May 2005 132 Tsetup Thold Parameter Min Tclk2out Tholdout ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet A9578-01 Max. Units Notes ns ns A9579-01 Document Number: 306261-002 ...

Page 133

... SMII_SYNC with respect to rising edge of 1 SMII_CLK SMII_TXD[4:0] and SMII_SYNC hold time after T 2 SMII_CLK. NOTES: 1. Timing was designed for a system load between 5pF and 15pF ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet Document Number: 306261-002 Parameter Min Parameter Min. 1.5 1 ...

Page 134

... SMII_TXCLK. NOTES: 1. Timing was designed for a system load between 5pF and 15pF May 2005 134 Parameter Min. 1 Parameter Min. 1.5 1.5 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet Max. Units Notes Max. Units Notes 5 ns ...

Page 135

... ETH_TXCLK. NOTES: 1. These values satisfy t the MII specification requirement clock to output delay. 2. Timing was designed for a system load between 5 pF and 15 pF. ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet Document Number: 306261-002 Parameter T 1 Parameter Electrical Specifications ...

Page 136

... The T4 input hold timing parameter is not 100% tested and is guaranteed by design. 5.6.2.5 MDIO Figure 27. MDIO Output Timings ETH_MDC ETH_MDIO NOTE: Processor is sourcing MDIO. May 2005 136 T 3 Parameter Min. 5 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet T 4 A9581-01 Max. Units Notes A9582-02 Document Number: 306261-002 ...

Page 137

... Timing was designed for a system load between 5pF and 20pF 5.6.2.6 DDRI SDRAM Bus Figure 29. DDRI SDRAM Write Timings DDRI_M_CLK ADDR/CTRL DDRI_DQS DDRI_DQ, _CB, _DM ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet Document Number: 306261-002 Parameter Min ...

Page 138

... The period to period clock jitter on each DDRI_M_CLK pair is spec’ed at +/-100ps. Figure 30. DDRI SDRAM Read Timings (2.0 CAS Latency) DDRI_M_CLK DDRI_DQS DDRI_RCVENOUT_N DDRI_RCVENIN_N DDRI_DQ, _CB, _DM May 2005 138 Parameter Min. 1.5 1.5 1.0 1 CMD D0 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet Max. Units Notes 1 1 ...

Page 139

... DDRI data 5 signals can operate with the memory controller on the IXP45X/IXP46X network processors. NOTES: 1. Designed to JEDEC specification recommended that IBIS models be used to verify signal integrity on individual designs ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet Document Number: 306261-002 ...

Page 140

... EX_control_signals input signals consist of EX_ADDR, EX_CS_N, EX_SLAVE_CS_N, EX_REQ_GNT_N, EX_REQ_N, EX_BURST, EX_RD_N, EX_WR_N May 2005 140 EX_CLK Low Drive Med Drive Min. Max. Min 0.5 0.5 3.5 3.5 0.5 0.5 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet Drive Units Notes Max. Min. Max 8.5 6 ...

Page 141

... EX_ADDR EX_ALE EX_WR_N EX_DATA EX_RD_N EX_DATA Table 66. Intel Multiplexed Mode Values (Sheet Symbol Talepulse Pulse width of ALE (ADDR is valid at the rising edge of ALE) Tale2addrhold Valid address hold time after from falling edge of ALE Tdval2valwrt Write data valid prior to WR_N falling edge ...

Page 142

... Electrical Specifications Table 66. Intel Multiplexed Mode Values (Sheet Symbol Trdsetup Data valid required before the rising edge of RD_N Trdhold Data hold required after the rising edge of RD_N Time needed between successive accesses on expansion Trecov interface. NOTES: 1. The EX_ALE signal is extended form nnsec based on the programming of the T1 timing parameter. ...

Page 143

... Table 67. Intel Simplex Mode Values Symbol Parameter T Valid address to valid chip select addr2valcs T Write data valid prior to EXPB_IO_WRITE_N falling edge dval2valwrt T Pulse width of the EXP_IO_WRITE_N wrpulse T Valid data after the rising edge of EXPB_IO_WRITE_N dholdafterwr Data valid required before the rising edge of ...

Page 144

... T alepulse T ale2valcs Valid Address T dspulse T dval2valds T ale2addrhold Multiplexed Address/Data Output Data Address T rdsetup Address Input Data ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet T4 T5 1-4 Cycles 1-16 Cycles T recov T dhold2afterds T rdhold A9587-01 Min. Max. Units Notes ...

Page 145

... Clock to output delay for all signals will be a maximum for devices requiring operation in synchronous mode. 9. Timing was designed for a system load between 5pF and 60pF for high drive setting ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet Document Number: 306261-002 Electrical Specifications Min. ...

Page 146

... Cycles 1-4 Cycles 1-16 Cycles T ad2valcs Valid Address T dspulse T dval2valds Output Data T rdsetup Input Data ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet T4 T5 1-4 Cycles 1-16 Cycles T recov T dhold2afterds T rdhold A9588-01 Min. Max. Units Notes ...

Page 147

... EX_CLK EX_CS_N (hcs_n) EX_ADDR[2:1] (hcntl) EX_RD_N (hr_w_n) EX_ADDR[0] (hbil) Tcs2hds1val EX_W R_N (hds1_n) EX_RDY_N (hrdy) EX_DATA (hdin) ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet Document Number: 306261-002 Trecov Tadd_setup Valid Thds1_pulse Tdata_hold Tdata_setup Data Electrical Specifications Min ...

Page 148

... Timing was designed for a system load between 5 pF and 60 pF for high drive setting. May 2005 148 Description Min Address Timing Setup/Chip Select Timing Strobe Timing Hold Timing Recovery Phase Parameter ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet Max Unit Notes 3 4 Cycles Cycles ...

Page 149

... HRDY is de-active 6. One cycle is the period of the Expansion Bus clock. 7. Timing was designed for a system load between 5pF and 60pF for high drive setting ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet Document Number: 306261-002 Parameter Min. ...

Page 150

... Timing was designed for a system load between 5pF and 60pF for high drive setting May 2005 150 Tadd_setup Valid Thds1_pulse Tdata_setup Tdata_hold Data Parameter ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet Trecov Valid Data Min. Max. Units Notes 11 45 Cycles ...

Page 151

... HPI*-16 Multiplexed Read Mode EX_CLK EX_CS_N (hcs_n) EX_ADDR[2:1] (hcntl) EX_RD_N (hr_w_n) Tcs2hds1val EX_WR_N (hds1_n) EX_RDY_N (hrdy) EX_DATA (hdout) ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet Document Number: 306261-002 Tadd_setup Valid Thds1_pulse Tdata_setup Valid Data Electrical Specifications ...

Page 152

... EX_RD_N (hr_w_n) Tcs2hds1val EX_WR_N (hds1_n) EX_RDY_N (hrdy) EX_DATA (hdout) May 2005 152 Parameter Tadd_setup Valid Thds1_pulse Tdata_setup Valid Data ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet Min. Max. Units Notes 11 45 Cycles Cycles Cycles Cycles Cycles ...

Page 153

... HRDY is de-active 6. One cycle is the period of the Expansion Bus clock. 7. Timing was designed for a system load between 5 pF and 60 pF for high drive setting ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet Document Number: 306261-002 Electrical Specifications Parameter Min ...

Page 154

... HPI*-16 Non-Multiplexed Write Mode EX_CLK EX_CS_N (hcs_n) EX_ADDR[23:0] (ha) EX_RD_N (hr_w_n) Tcs2hds1val EX_WR_N (hds1_n) EX_RDY_N (hrdy) EX_DATA (hdin) May 2005 154 Tadd_setup Valid Thds1_pulse Tdata_hold Tdata_setup Data ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet Trecov Valid Data Document Number: 306261-002 ...

Page 155

... EX_RD_N EX_DATA NOTE: Notice that the access is an Intel-style simplex read access. The data strobe phase is set to a value to last three clock cycles. The data is returned from the peripheral device prior to the three clocks and the peripheral device de-asserts EX_IOWAIT_N. The data strobe phase terminates after two clocks even though the strobe phase was configured to pulse for three clocks. ® ...

Page 156

... Clock jitter on the SSPSCLK is designed average of the specified clock frequency. The SSPSCLK jitter specification is unspecified. May 2005 156 T OV SSPEXT CLK SSPSCLK T IS SSPINPUT S Parameter ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet Min. Max. Units Notes .0072 1.8432 MHz ...

Page 157

... SR T SCL and SDA Fall Time SF T Setup Time for STOP Condition SUSTO NOTES: 1. Not tested 2. After this period, the first clock pulse is generated ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet Document Number: 306261-002 T BUF LOW SR T ...

Page 158

... May 2005 158 Valid Data Valid Data Valid Data Valid Data ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet T9 A9594-01 Document Number: 306261-002 ...

Page 159

... MHz. The clock duty cycle accepted will be 50/50 + 20%. 6. Timing was designed for a system load between 5 pF and 30 pF for high drive setting ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet Document Number: 306261-002 Parameter 1/8 ...

Page 160

... JTG_TCK may be stopped indefinitely in either the low or high phase. May 2005 160 T bsel JTG_TCK T bsis JTG_TDO T bsoh T bsod JTG_TRST_N T bsr JTG_TMS T T bsrs bsrh Parameter Conditions ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet T bsch T bsih B0416-01 A9597-01 Min. Typ. Max. Units 1 ...

Page 161

... The expansion bus address is captured as a derivative of the RESET_IN_N signal going high. When a programmable-logic device is used to drive the EX_ADDR signals instead of pull-downs, the signals must be active until PLL_LOCK is active. ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet Document Number: 306261-002 CFG Settings To Be Captured ...

Page 162

... IO_PHASE POWER_UP TIME ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet must be powered up at least 1 µs CCM) ) must the 2.5-V I/O voltage (V ). CCM power-up pattern. The CC and V . The CCP CCM at 3 ...

Page 163

... Current measurements are average and not peak. ® 5. Intel XScale Core processor tested running DSP software. 5.9 Ordering Information For ordering information, please contact your local Intel sales representative. ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet ...

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