GWIXP460BADT Intel, GWIXP460BADT Datasheet - Page 37
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GWIXP460BADT
Manufacturer Part Number
GWIXP460BADT
Description
Manufacturer
Intel
Datasheet
1.GWIXP460BADT.pdf
(163 pages)
Specifications of GWIXP460BADT
Core Operating Frequency
533MHz
Operating Supply Voltage (typ)
1.3/1.5/2.5/3.3V
Operating Supply Voltage (max)
1.575/2.7/3.465V
Operating Supply Voltage (min)
1.235/2.3/3.135V
Package Type
BGA
Pin Count
544
Mounting
Surface Mount
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Lead Free Status / Rohs Status
Not Compliant
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3.2.6
3.2.7
3.2.8
Intel
Document Number:
®
IXP45X and Intel
Data Cache
The Data Cache (D-Cache) can contain high-use data such as lookup tables and filter coefficients,
allowing the core access to data at core frequencies. This prevents core stalls caused by multi-cycle
accesses to external memory.
The 32-Kbyte D-cache is 32-set/32-way associative, where each set contains 32 ways and each
way contains a tag address, a cache line (32 bytes with one parity bit per byte) of data, two dirty
bits (one for each of two eight-byte groupings in a line), and one valid bit. For each of the 32 sets,
zero through 28 ways can be locked, unlocked, or used as local SRAM. Unlocked ways are
replaceable via a round-robin policy.
The D-cache (together with the mini-data cache) can be enabled or disabled. Attribute bits within
the descriptors, contained in the DTLB of the DMMU, provide significant control over an enabled
D-cache. These bits specify cache operating modes such as read and write allocate, write-back,
write-through, and D-cache versus mini-data cache targeting.
The D-cache (and mini-data cache) work with the load buffer and pend buffer to provide “hit-
under-miss” capability that allows the core to access other data in the cache after a “miss” is
encountered. The D-cache (and mini-data cache) works in conjunction with the write buffer for
data that is to be stored to memory.
Mini-Data Cache
The mini-data cache can contain frequently changing data streams such as MPEG video, allowing
the core access to data streams at core frequencies. This prevents core stalls caused by multi-cycle
accesses to external memory. The mini-data cache relieves the D-cache of data “thrashing” caused
by frequently changing data streams.
The 2-Kbyte, mini-data cache is 32-set/two-way associative, where each set contains two ways and
each way contains a tag address, a cache line (32 bytes with one parity bit per byte) of data, two
dirty bits (one for each of two eight-byte groupings in a line), and a valid bit. The mini-data cache
uses a round-robin replacement policy, and cannot be locked.
The mini-data cache (together with the D-cache) can be enabled or disabled. Attribute bits
contained within a coprocessor register specify operating modes write and/or read allocate, write-
back, and write-through.
The mini-data cache (and D-cache) work with the load buffer and pend buffer to provide “hit-
under-miss” capability that allows the core to access other data in the cache after a “miss” is
encountered. The mini-data cache (and D-cache) works in conjunction with the write buffer for
data that is to be stored to memory.
Fill Buffer and Pend Buffer
The four-entry fill buffer (FB) works with the core to hold non-cacheable loads until the bus
controller can act on them. The FB and the four-entry pend buffer (PB) work with the D-cache and
mini-data cache to provide “hit-under-miss” capability, allowing the core to seek other data in the
caches while “miss” data is being fetched from memory.
306261-002
®
IXP46X Product Line of Network Processors Datasheet
Functional Overview
May 2005
37
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