GWIXP460BADT Intel, GWIXP460BADT Datasheet - Page 38
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GWIXP460BADT
Manufacturer Part Number
GWIXP460BADT
Description
Manufacturer
Intel
Datasheet
1.GWIXP460BADT.pdf
(163 pages)
Specifications of GWIXP460BADT
Core Operating Frequency
533MHz
Operating Supply Voltage (typ)
1.3/1.5/2.5/3.3V
Operating Supply Voltage (max)
1.575/2.7/3.465V
Operating Supply Voltage (min)
1.235/2.3/3.135V
Package Type
BGA
Pin Count
544
Mounting
Surface Mount
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Lead Free Status / Rohs Status
Not Compliant
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Functional Overview
3.2.9
3.2.10
May 2005
38
The FB can contain up to four unique “miss” addresses (logical), allowing four “misses” before the
core is stalled. The PB holds up to four addresses (logical) for additional “misses” to those
addresses that are already in the FB. A coprocessor register can specify draining of the fill and pend
(write) buffers.
Write Buffer
The write buffer (WB) holds data for storage to memory until the bus controller can act on it. The
WB is eight entries deep, where each entry holds 16 bytes. The WB is constantly enabled and
accepts data from the core, D-cache, or mini-data cache.
Coprocessor 15, Register 1 specifies whether WB coalescing is enabled or disabled. When
coalescing is disabled, stores to memory occur in program order — regardless of the attribute bits
within the descriptors located in the DTLB.
When coalescing is enabled, the attribute bits within the descriptors located in the DTLB are
examined to determine when coalescing is enabled for the destination region of memory. When
coalescing is enabled in both CP15, R1 and the DTLB, data entering the WB can coalesce with any
of the eight entries (16 bytes) and be stored to the destination memory region, but possibly out of
program order.
Stores to a memory region specified to be non-cacheable and non-bufferable by the attribute bits
within the descriptors located in the DTLB causes the core to stall until the store completes. A
coprocessor register can specify draining of the write buffer.
Multiply-Accumulate Coprocessor
For efficient processing of high-quality, media-and-signal-processing algorithms, the Multiply-
Accumulate Coprocessor (CP0) provides 40-bit accumulation of 16 x 16, dual-16 x 16 (SIMD),
and 32 x 32 signed multiplies. Special MAR and MRA instructions are implemented to move the
40-bit accumulator to two core-general registers (MAR) and move two core-general registers to the
40-bit accumulator (MRA). The 40-bit accumulator can be stored or loaded to or from D-cache,
mini-data cache, or memory using two STC or LDC instructions.
The 16 x 16 signed multiply-accumulates (MIAxy) multiply either the high/high, low/low, high/
low, or low/high 16 bits of a 32-bit core general register (multiplier) and another 32-bit core
general register (multiplicand) to produce a full, 32-bit product that is sign-extended to 40 bits and
added to the 40-bit accumulator.
Dual-signed, 16 x 16 (SIMD) multiply-accumulates (MIAPH) multiply the high/high and low/low
16-bits of a packed 32-bit, core-general register (multiplier) and another packed 32-bit, core-
general register (multiplicand) to produce two 16-bits products that are both sign-extended to
40 bits and added to the 40-bit accumulator.
The 32 x 32 signed multiply-accumulates (MIA) multiply a 32-bit, core-general register
(multiplier) and another 32-bit, core-general register (multiplicand) to produce a 64-bit product
where the 40 LSBs are added to the 40-bit accumulator. The 16 x 32 versions of the 32 x 32
multiply-accumulate instructions complete in a single cycle.
Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors Datasheet
Document Number:
306261-002
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