72T7285L4-4BB IDT, Integrated Device Technology Inc, 72T7285L4-4BB Datasheet - Page 18

• Manufacturer Part Number: 72T7285L4-4BB
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 72T7285L4-4BB

• Configuration: Dual
• Density: 1.125Mb
• Access Time (max): 3.4ns
• Word Size: 72b
• Organization: 16Kx72
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: BGA
• Clock Freq (max): 225MHz
• Operating Supply Voltage (typ): 2.5V
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (max): 2.625V
• Supply Current: 130mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / Rohs Status: Not Compliant

NOTE:
1. Consecutive reads of the offset registers is not permitted. The read operation must be disabled for a minimum of one RCLK cycle in between offset register accesses. (Please
IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync™ ™ ™ ™ ™ 72-BIT FIFO
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
refer to Figure 22, Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes) for more details).
D/Q17 D/Q16
D/Q17
D/Q17 D/Q16
D/Q17
D/Q35
D/Q35
D/Q71
D/Q71
1st Parallel Offset Write/Read Cycle
2nd Parallel Offset Write/Read Cycle
3rd Parallel Offset Write/Read Cycle
4th Parallel Offset Write/Read Cycle
D/Q16
D/Q16
16
16
16
15
16
15
15
14
15
14
D/Q19
D/Q19
D/Q19
EMPTY OFFSET (LSB) REGISTER (PAE)
FULL OFFSET (LSB) REGISTER (PAF)
D/Q19
EMPTY OFFSET (MSB) REGISTER (PAE)
FULL OFFSET (MSB) REGISTER (PAF)
14
13
14
13
Figure 3. Programmable Flag Offset Programming Sequence (Continued)
D/Q17
13
13
12
D/Q17
12
D/Q17
D/Q17
17
17
17
17
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
1st Parallel Offset Write/Read Cycle
2nd Parallel Offset Write/Read Cycle
1st Parallel Offset Write/Read Cycle
2nd Parallel Offset Write/Read Cycle
12
11
11
12
16
16
16
17
16
17
17
17
EMPTY OFFSET REGISTER (PAE)
11
EMPTY OFFSET REGISTER (PAE)
11
10
10
16
15
FULL OFFSET REGISTER (PAF)
16
15
16
15
FULL OFFSET REGISTER (PAF)
15
16
10
10
9
14
9
14
15
15
14
15
14
15
D/Q8
D/Q8
x18 Bus Width
9
14
13
14
13
14
13
9
14
13
8
8
13
13
12
8
8
13
12
13
12
12
7
7
12
11
12
11
11
7
12
12
7
11
x36 Bus Width
x72 Bus Width
6
6
11
10
6
6
11
11
10
11
10
10
# of Bits Used
5
5
10
5
10
5
10
10
9
9
9
9
D/Q8
D/Q8
D/Q8
D/Q8
4
4
4
4
9
9
9
9
3
3
3
3
8
8
8
8
8
8
8
8
2
2
2
2
7
7
7
7
7
7
7
7
# of Bits Used
# of Bits Used
18
# of Bits Used
# of Bits Used
D/Q0
D/Q0
D/Q0
D/Q0
17
17
17
17
1
1
1
1
6
6
6
6
6
6
6
6
5
5
5
5
5
5
5
5
Non-Interspersed
Parity
Interspersed
Parity
4
4
4
4
4
4
4
4
3
3
3
3
3
3
3
3
2
2
2
2
2
2
2
2
D/Q0
D/Q0
D/Q0
D/Q0
1
1
1
1
1
1
1
1
Non-Interspersed
Parity
Non-Interspersed
Parity
Non-Interspersed
Parity
Interspersed
Parity
Non-Interspersed
Parity
Interspersed
Parity
Interspersed
Parity
Interspersed
Parity
# of Bits Used:
14 bits for the IDT72T7285
15 bits for the IDT72T7295
16 bits for the IDT72T72105
17 bits for the IDT72T72115
Note: All unused input bits
are don’t care.
COMMERCIAL AND INDUSTRIAL
5994 drw07
TEMPERATURE RANGES