MT4JSF12864HZ-1G1D1 Micron Technology Inc, MT4JSF12864HZ-1G1D1 Datasheet - Page 4

• Manufacturer Part Number: MT4JSF12864HZ-1G1D1
• Description: MOD DDR3 SDRAM 1GB 200SODIMM
• Manufacturer: Micron Technology Inc
• Series: -r

Specifications of MT4JSF12864HZ-1G1D1

• Main Category: DRAM Module
• Sub-category: DDR3 SDRAM
• Module Type: SODIMM
• Device Core Size: 64b
• Organization: 128Mx64
• Total Density: 1GByte
• Maximum Clock Rate: 1.066GHz
• Operating Supply Voltage (typ): 1.5V
• Operating Current: 840mA
• Number Of Elements: 4
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 204
• Mounting: Socket
• Memory Type: DDR3 SDRAM
• Memory Size: 1GB
• Speed: 1066MT/s
• Features: -
• Package / Case: 200-SODIMM
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Table 6: Pin Descriptions
PDF: 09005aef83b05507
jsf4c64_128x64hz.pdf - Rev. B 3/10
RAS#, CAS#,
CK0, CK0#
DQS#[7:0]
DQS[7:0],
DQ[63:0]
Symbol
DM[7:0]
EVENT#
BA[2:0]
A[13:0]
RESET#
SA[1:0]
V
V
ODT0
CKE0
WE#
SDA
V
DDSPD
S0#
SCL
REFCA
DD
(open drain)
(LVCMOS)
Output
Supply
Supply
Supply
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Type
I/O
I/O
I/O
Description
Address inputs: Provide the row address for ACTIVATE commands, and the column ad-
dress and auto precharge bit (A10) for READ/WRITE commands, to select one location out
of the memory array in the respective bank. A10 is sampled during a PRECHARGE com-
mand to determine whether the PRECHARGE applies to one bank (A10 LOW, bank selected
by BA[2:0]) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selec-
ted by BA. A12 is also used for BC4/BL8 identification as “BL on-the-fly” during CAS
commands. The address inputs also provide the op-code during the mode register com-
mand set. A[12:0] address the 1Gb DDR3 devices. A[13:0] address the 2Gb devices.
Bank address inputs: BA[2:0] define the device bank to which an ACTIVATE, READ,
WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode register
(MR0, MR1, MR2, and MR3) is loaded during the LOAD MODE command.
Clock: CK and CK# are differential clock inputs. All control, command, and address input
signals are sampled on the crossing of the positive edge of CK and the negative edge of CK#.
Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal circui-
try and clocks on the DRAM.
Data input mask: DM is an input mask signal for write data. Input data is masked when
DM is sampled HIGH, along with the input data, during a write access. DM is sampled on
both edges of DQS. Although DM pins are input-only, the DM loading is designed to match
that of DQ and DQS pins.
On-die termination: ODT (registered HIGH) enables termination resistance internal to the
DDR3 SDRAM. When enabled, ODT is only applied to the following pins: DQ, DQS, DQS#,
and DM. The ODT input will be ignored if disabled via the LOAD MODE command.
Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being en-
tered.
Reset: An active LOW CMOS input referenced to V
input defined as a rail-to-rail signal with DC HIGH ≥ 0.8 × V
Chip select: S# enables (registered LOW) and disables (registered HIGH) the command de-
coder.
Presence-detect address inputs: These pins are used to configure the temperature sensor/
SPD EEPROM address range on the I
Serial clock for presence-detect: SCL is used to synchronize communication to and from
the temperature sensor/SPD EEPROM.
Data input/output: Bidirectional data bus.
Data strobe: DQS and DQS# are differential data strobes. Output with read data. Edge-
aligned with read data. Input with write data. Center-aligned with write data.
Serial data: SDA is a bidirectional pin used to transfer addresses and data into and out of
the temperature sensor/SPD EEPROM on the I
Temperature event: The EVENT# pin is asserted by the temperature sensor when critical
temperature thresholds have been exceeded.
Power supply: 1.5V ±0.075V.
Serial EEPROM positive power supply: +3.0V to +3.6V.
Reference voltage: Control, command, and address (V
512MB, 1GB (x64, SR) 204-Pin DDR3 SODIMM
4
2
C bus.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
Pin Assignments and Descriptions
2
C bus.
SS
. The RESET# input receiver is a CMOS
DD
/2).
DD
and DC LOW ≤ 0.2 × V
© 2009 Micron Technology, Inc. All rights reserved.
DD
.