STA330 STMicroelectronics, STA330 Datasheet
STA330
Specifications of STA330
Related parts for STA330
STA330 Summary of contents
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... Individual channel and master gain/attenuation ! Automatic invalid-input detect mute Table 1. Device summary Order code STA330 STA33013TR December 2007 2.0 digital audio processor ! 2-channel serial input/output data interface ! Digitally controlled pop-free operation Package VFQFPN52 VFQFPN52 Rev 1 STA330 VFQFPN52 Packaging Tube Tape and reel 1/55 www.st.com 1 ...
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... Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.2 Configuration examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7 Analog-digital converter (ADC 7.1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.1.1 7.1.2 7.1.3 7.2 Application scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.3 Configuration examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8 Serial digital audio interface (SAI 8.1 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2/55 Digital anti-aliasing filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 21 High-pass filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Programmable gain amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 STA330 ...
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... STA330 8.2 Master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.3 Slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.4 Serial formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.4.1 8.4.2 8.4.3 8.4.4 8.5 SAI pass-through . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9.1 Data transition and change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9.2 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9.3 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9.4 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9.5 Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9.6 Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9.6.1 9.6.2 9.7 Read operation ...
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... Introduction 1 Introduction The STA330 is a digital stereo audio processor with analog and digital input. It includes an audio DSP and FFX proprietary high-efficiency class-D driver. In conjunction with a power device, the STA330 provides high-quality digital amplification. The STA330 contains an on-chip volume/gain control. The PWM amplifier achieves greater than 90% efficiency for longer battery life for portable systems ...
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... STA330 2 Connection diagrams and pin descriptions 2.1 Connection diagram Figure 2. Pin out (package underside view Connection diagrams and pin descriptions 27 VFQFPN52 Exposed pad down Exposed pad 5/55 ...
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... PWM output Channel 2 PWM B output Ground Channel 2 PWM B power ground Ground Channel 2 PWM A power ground PWM output Channel 2 PWM A output Supply Channel 2 PWM A power supply Ground Pre-driver ground Ground I/O ring ground Supply I/O ring supply Supply Pre-driver supply STA330 Description ...
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... STA330 Table 2. Pin list (continued) Pin # Name POWERFAULT/ 31 EAPD I2CDIS 34 SCL 35 SDA 36 SELCLK33 37 MCLK33 38 XTI 39 XTO 40 FILT 41 GNDPLL 42 VDDPLL 43 GND2 44 VDD2 45 SDATAI 46 SDATAO 47 LRCLKI 48 LRCLKO 49 GNDIO2 50 VDDIO2 51 BICLKI 52 BICLKO EP Connection diagrams and pin descriptions Type Power fault signal (active high) / Digital output ...
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... Storage temperature Ambient operating temperature Parameter Digital supply voltage ADC supply voltage PLL analog supply voltage Power stage supply voltage Pre-driver supply voltage Channel 1 and 2 power ground, pre-driver ground Ambient operating temperature STA330 Min Max Unit -0.5 +4.0 V -0.5 +4.0 V -0.5 +4 ...
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... STA330 3.2 Electrical characteristics Table 5 lists the device electrical characteristics under the conditions nominal supply voltage (see Table 4), LRCLKI frequency (f unless otherwise specified. Table 5. Electrical characteristics Symbol Parameter Logic power supply current at IstbyL standby Logic power supply current at IddL operating Tds ...
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... Deviation from linear phase Pass band Pass band ripple Stop band Stop band attenuation Group delay, 8 kHz Group delay, 48 kHz Cross talk, 1.8 V Cross talk, 3.3 V 10/ junction temperature. Parameter 200 µs Parameter STA330 on page 18, a Value Min Typ Max Unit ...
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... STA330 4 Applications Figure 3 to Figure 6 STA510F. Figure 3. STA330 codec block Figure 4. STA510F power stage block below show the circuit diagrams of a typical application with the IC401 IC - STA510F Applications PWM output selection Binary, Ternary 11/55 ...
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... Direct control and settings block Table 8. Components for setting up application Component R413 No R28 Yes R12 Yes R21 No R11 Yes R18 No R17 Yes 12/55 µController µLess Yes No Yes No Yes No Yes Comments EAPD (µLess mode) POWERFAULT -> EAPD (µP mode) STA510F: PWM1B STA510F: PWM1A STA510F: PWM2B STA330 ...
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... STA330 Table 8. Components for setting up application (continued) Component R25 No R16 Yes R22 No J7 2-3 J6 2-3 J5 2-3 J4 2-3 (L) µController µLess No Yes No 1-2 1-2 2-3 1-2 (H) Applications Comments STA510F: PWM2A Volume up (µLess mode) Volume down (µLess mode) 3.3-V supply I2CDIS 13/55 ...
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... Digital processing 5 Digital processing The STA330 processor block is a digital block providing two channels of audio processing and channel-mapping capability. 5.1 Signal processing flow stereo ADC data can be selected. The I ADC sampling frequency can be selected from 8 kHz to 48 kHz interface disabled When pin I2CDIS = 1, the SDA, SCL, LRCLKO and BICLKO pins can be pulled high or low to change certain parameters of operation ...
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... STA330 5.3 Volume control and gain The volume control structure of the STA330 consists of individual volume registers for each channel and a master volume register that provides an offset to each channel’s volume setting. The individual channel volumes are adjustable in 0.5 dB steps from + -91.5 dB example, if register LVOL = 0x00 or +36 dB and register MVOL = 0x18 or -12 dB, then the total gain for the left channel is +24 dB ...
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... STRB_ BYPASS FRAC_CTRL DITHER_DISABLE 16/55 INFIN Input frequency FBCLK divider INFIN Phase / frequency Buffer divider (PFD) FBCLK Loop frequency divider Fractional controller FRAC_INPUT NDIV STA330 LOCKP Lock detect FILT LF Charge pump and VCONT loop filter VCO F VCO Output PHI frequency divider ...
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... Output frequency divider The PLL output PHI is generated by dividing the F The divider that divides the F frequency divider. In the STA330, the ODF is fixed to be divisible by 2 and cannot be configured. Lock-detect circuit The output of this block (the LOCKP signal) is asserted high when the PLL enters the state of COARSE LOCK in which the output frequency is within ± ...
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... C1 = 250 pF, and pF. Figure 8. PLL filter scheme Table 6 on page 10 6.2 Configuration examples The STA330 PLL can be configured in two ways: " default startup configuration " direct PLL programming The default startup configuration reads the device defaults. With this configuration not necessary to program the PLL dividers directly as some presets are used. In this mode, the oversampling ratio between pins XTI (or MCLK33) and LRCLKI is fixed to 256 ...
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... STA330 If register bit PLLCFG0.FRAC_CTRL = 0, then VCO INFIN PHI VCO In the above equations: FRACT = Decimal equivalent of register bit PLLCFG1.FRAC_INPUT[15:0] IDF = Input division factor (refer to previous formulas) LDF = Loop division factor (refer to previous formulas) ODF = Output division factor = INFIN frequency INFIN F = XTI frequency ...
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... IDF should be equal to 4 otherwise LDF become less than 8 (FRAC_CTRL must be 1): LDF = floor(49.152 / (19.2 / IDF FRACT = round([(49.152 / (19.2 / IDF)) - floor(49.152 / (19.2 / IDF))] * 2 Using the above configuration, the system clock is 49.151953125 MHz, the approximate static error (that is, 1 ppm). 20/55 STA330 27602 15728 ...
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... Analog-digital converter (ADC) 7.1 Functional description The STA330 analog input is provided through a low-power, low-voltage, stereo, audio-ADC front end designed for audio applications. It includes a programmable gain amplifier, anti- aliasing filter, a low-noise microphone biasing circuit, a third-order, MASH2-1, delta-sigma modulator, a digital decimating filter and a first-order DC-removal filter. This device is fabricated using a 0 ...
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... INL C0 INR AVDD C5 AGND VHI C6 VLO VCM C7 VBIAS C8 STA330 Typical µF C6 µF (low ESR and ESL capacitors are recommended) The VSSA plane must be a different plane to the other ground planes The 3-V, 3-A supply must be low-noise and separate from the other supplies Ω ...
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... STA330 7.3 Configuration examples The ADC sampling frequency can be selected from three values: " normal (from 32 kHz to 48 kHz) " low (from 16 kHz to 24 kHz) " very-low (from 8 kHz to 12 kHz). The setting is done through bits ADC_FS_RANGE in register other settings, register ADCCFG on page 47 is used ...
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... Symbol LRCLKI/LRCLKO propagation delay from BICLK active t DL edge t SDATAI propagation delay from BICLKI/O active edge DDA t Sdatao setup time to BICLKI/O strobing edge DST t Sdatao hold time from BICLKI/O strobing edge DHT 24/ DST DHT Parameter STA330 DDA Min Typ Max Unit ...
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... STA330 8.3 Slave mode In this mode, pins BICLKI/O and pins LRCLKI/O are configured as inputs. Figure 11. Slave mode BICLKI/ BICLKO LRCLKI/ LRCLKO SDATAO SDATAI Table 15. Slave mode Symbol t BICLK cycle time BCY t BICLK pulse width high BCH t BICLK pulse width low BCL ...
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... Different audio formats are supported in both master and slave modes. Clock and data configurations can be customized to match most of the serial audio protocols available on the market. Data length can be customized for 8-, 16-, 24- and 32-bit. Figure 12. Right justified LRCLKI/ LRCLKO BICLKI/ BICLKO SDATAI/ SDATAO Figure 13. Left justified LRCLKI/ LRCLKO BICLKI/ BICLKO SDATAI SDATAO 26/ STA330 ...
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... STA330 8.4.1 DSP Figure 14. DSP LRCLKI/ LRCLKO BICLKI/ BICLKO SDATAI/ SDATAO 2 8.4 Figure 15 LRCLKI/ LRCLKO BICLKI/ BICLKO SDATAI/ SDATAO Left Serial digital audio interface (SAI) Right 27/55 ...
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... PCM/IF (non-delayed mode) " MSB first " 16-bit data Figure 16. PCM/IF (non-delayed mode) LRCLKI/ LRCLKO BICLKI/ BICLKO SDATAI SDATAO 8.4.4 PCM/IF (delayed mode) " MSB first " 16-bit data Figure 17. PCM/IF (delayed mode) LRCLKI/ LRCLKO BICLKI/ BICLKO SDATAI/ SDATAO 28/55 Any width STA330 ...
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... SAI pass-through A configuration is available which allows the SAI input signal to be passed straight to the digital output. The STA330 is able to translate the incoming serial audio interface signal from SAI- different output format on SAI-out. So the SAI pass-through enables devices to be cascaded, even devices with slightly different protocols. ...
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... Data input During data input, the STA330 samples the SDA signal on the rising edge of clock SCL. For correct device operation the SDA signal must be stable during the rising edge of the clock and the data can change only when the SCL line is low. ...
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... STA330 again responds with an acknowledgement. The master then initiates another start condition and sends the device select code with the R/W bit set to 1. The STA330 acknowledges this and then responds by sending one byte of data. The master then terminates the transfer by generating a stop condition. ...
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... Random address multi-byte read The multi-byte read modes could start from any internal address. Sequential data bytes are read from sequential addresses within the STA330. The master acknowledges each data byte read and then generates a stop condition terminating the transfer. 2 Figure 18 ...
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... STA330 10 Registers 10.1 Summary Table 16. Register summary Address Name Bit 7 0x00 FFXCFG0 MUTE 0x01 FFXCFG1 L1_R2 0x02 MVOL 0x03 LVOL 0x04 RVOL 0x05 TTF0 0x06 TTF1 0x07 TTP0 0x08 TTP1 BICLK_ 0x0A S2PCFG0 STRB 0x0B S2PCFG1 PDATA_LENGTH[1:0] BICLK_ 0x0C P2SCFG0 STRB ...
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... Default is 666.66 µs 34/55 Bit 6 Bit 5 Bit 4 Reserved Reserved PWM_INT[15:8] PWM_INT[7:0] POW_ POW_ POW_ TRISTATE FAULT1A FAULT1B FFX configuration register 0 Bit 5 Bit 4 Bit 3 BIN_ SOFTSTART * 20.83 µs Bit 3 Bit 2 Bit 1 POW_ POW_ FAULT2A FAULT2B Bit 2 Bit 1 TIM_SOFT_VOL[3:0] 1: FFX output is zero STA330 Bit 0 Bit 0 ...
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... STA330 FFXCFG1 Bit 7 Bit 6 MUTE_ON_ L1_R2 INVALID Address: 0x01 Type: R/W Buffer: No Reset: 0xF8 Description: 7 L1_R2: channel mapping: 0: right channel is mapped to output channel 1 and left channel is mapped to output channel 2 1: left channel is mapped to output channel 1 and right channel is mapped to output channel 2 (default) ...
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... SET_VOL_RIGHT[7:0]: right channel volume control: Right channel volume control (from + -91 0.5 dB steps) Default value (0x48) corresponds 36/55 Left channel volume control Bit 5 Bit 4 Bit 3 SET_VOL_LEFT[7:0] Right channel volume control Bit 5 Bit 4 Bit 3 SET_VOL_RIGHT[7:0] STA330 Bit 2 Bit 1 Bit 0 Bit 2 Bit 1 Bit 0 ...
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... STA330 TTF0 Bit 7 Bit 6 Address: 0x05 Type: R/W Buffer: No Reset: 0x00 Description: 7:0 MSBs of TIM_TS_FAULT[15:0]: See TTF1 on page TTF1 Bit 7 Bit 6 Address: 0x06 Type: R/W Buffer: No Reset: 0x02 Description: 7:0 LSBs of TIM_TS_FAULT[15:0]: time in which power is held in tri-state mode after a fault signal: Time is TIM_TS_FAULT * 83.33 µ ...
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... LSBs of TIM_TS_POWUP[15:0]: time in which power is held in tri-state mode after a power-up signal: Time is TIM_TS_POWUP * 83.33 µs Default value(0x0002) corresponds to 166.66 µs tri-state time after power-up 38/55 Tri-state time-after-power-up register 0 Bit 5 Bit 4 Bit 3 TIM_TS_POWUP[15:8] Tri-state time-after-power-up register 1 Bit 5 Bit 4 Bit 3 TIM_TS_POWUP[7:0] STA330 Bit 2 Bit 1 Bit 0 Bit 2 Bit 1 Bit 0 ...
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... STA330 S2PCFG0 Bit 7 Bit 6 BICLK_STRB LRCLK_LEFT SHARE_BILR Address: 0x0A Type: R/W Buffer: No Reset: 0xD2 Description: 7 BICLK_STRB: 0: bit clock strobe edge is falling edge, bit clock active edge is rising edge 1: bit clock strobe edge is rising edge, bit clock active edge is falling edge (default) ...
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... Value is (N+ 3:2 MAP_L[1:0]: left data-mapping slot: 00: slot0 (default) Value is nth slot 1:0 MAP_R[1:0]: right data-mapping slot: 01: slot1 (default) Value is nth slot 40/55 Serial-to-parallel audio interface config register 1 Bit 5 Bit 4 Bit 3 BICLK_OS[1:0] MAP_L[1:0] (where f = sampling frequency STA330 Bit 2 Bit 1 Bit 0 MAP_R[1:0] ...
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... STA330 P2SCFG0 Bit 7 Bit 6 BICLK_ STRB LRCLK_LEFT SDATAO_ACT Address: 0x0C Type: R/W Buffer: No Reset: 0xD3 Description: 7 BICLK_STRB: defines the bit clock edges: 0: strobe is falling edge, active edge is rising 1: strobe is rising edge, active edge is falling (default) 6 LRCLK_LEFT: defines the channel for the LR clock: ...
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... BICLK_OS[1:0]: bit clock oversampling: 01 (default) s Value is (BICLK_OS+ 3:2 MAP_L[1:0]: left data-mapping slot: 00: slot0 (default) Value is nth slot 1:0 MAP_R[1:0]: right channel data-mapping slot: 01: slot1 (default) Value is nth slot 42/55 Parallel-to-serial audio interface config register 1 Bit 5 Bit 4 Bit 3 BICLK_OS[1:0] MAP_L[1:0] s STA330 Bit 2 Bit 1 Bit 0 MAP_R[1:0] ...
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... STA330 PLLCFG0 Bit 7 Bit 6 PLL_DIRECT_ FRAC_CTRL PROG Address: 0x14 Type: R/W Buffer: No Reset: 0x00 Description: 7 PLL_DIRECT_PROG: PLL programming: 0: default 1: PLL is programmed according to the PLLCFG register settings 6 FRAC_CTRL: 0: default 1: PLL fractional-frequency synthesis is enabled 5:4 DITHER_DISABLE[1:0]: 00: default MSB = 1: disables rectangular PDF dither input to SDM ...
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... NDIV[5:0]: PLL multiplication factor (integral part) named as loop division factor: 00 00XX: LDF = NA 00 0101: LDF = 5 11 0111: LDF = 55 44/55 PLL configuration register 2 Bit 5 Bit 4 Bit 3 FRAC_INPUT[7:0] PLL configuration register 3 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 2 Bit 1 NDIV[5:0] 1: STRB signal is bypassed 00 0100: LDF = NA ... 11 1XXX: LDF = NA STA330 Bit 0 Bit 0 ...
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... STA330 PLLPFE Bit 7 Bit 6 PLL_BYP_UNL BICLK2PLL PLL_PWDN Address: 0x18 Type: R/W Buffer: No Reset: 0x00 Description: 7 PLL_BYP_UNL: PLL bypass: 0: PLL is not bypassed (default) 6 BICLK2PLL: 0: default 5 PLL_PWDN: 0: default 4 PFE1A: 0: default 1: pop-free resistances are connected to output 1A 3 PFE1B: 0: default 1: pop-free resistances are connected to output 1B ...
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... PLL_PWD_ STATE: PLL power-down state: 0: PLL is not in power-down state 5 PLL_BYP_STATE: PLL bypass state: 0: PLL is not in bypass state 4:0 Reserved 46/55 PLL status register (RO) Bit 5 Bit 4 Bit 3 PLL_ Bit 2 Bit 1 1: PLL is in unlock state 1: PLL is in power-down state 1: PLL is in bypass state STA330 Bit 0 ...
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... STA330 ADCCFG Bit 7 Bit 6 PGA[2:0] Address: 0x1E Type: RO Buffer: No Reset: Undefined Description: 7:5 PGA[2:0]: gain selection bits for the ADC programmable gain amplifier: 000: default Values are from steps 4 INSEL: 0: line input selected (default) 1: microphone input selected (INL is the input) 3 STBY: ADC standby mode: ...
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... FFX input is from ADC 0 CORE_CLKENBL: availability of system clock: 0: FFX system clock disabled 48/55 Miscellaneous configuration register Bit 5 Bit 4 Bit 3 ADC_FS_RANGE[1: kHz kHz) (default kHz) = 128 to 192 kHz kHz) (default kHz) s Bit 2 Bit 1 P2P_IN_ADC 1: disabled 1: FFX system clock enabled (default) STA330 Bit 0 CORE_ CLKENBL ...
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... STA330 FFXST Bit 7 Bit 6 Address: 0x23 Type: RO Buffer: No Reset: Undefined Description: 7:3 Reserved 2 INVALID_INP_FBK: invalid input status: 1: invalid input sent to FFX 1 MUTE_INT_FBK: FFX mute status 1: FFX is in mute state 0 Reserved PWMINT1 Bit 7 Bit 6 Address: 0x2D Type: R/W Buffer: No Reset: 0x00 Description: ...
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... POW_FAULT1A: 1: power bridge fault state 4 POW_FAULT1B: 1: power bridge fault state 3 POW_FAULT2A: 1: power bridge fault state 2 POW_FAULT2B: 1: power bridge fault state 1:0 Reserved 50/55 Power bridge status register Bit 5 Bit 4 Bit 3 POW_FAULT1B POW_FAULT2A Bit 2 Bit 1 POW_FAULT2B 1: power-down state STA330 Bit 0 ...
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... STA330 11 Package information In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These package have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label ...
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... STA330 Dimensions in inches Min Typical Max 0.031 0.035 0.039 0.001 0.002 0.026 0.039 0.010 0.007 0.009 0.012 0.310 0.315 0.320 0.108 ...
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... STA330 12 Trademarks and other acknowledgements FFX is a STMicroelectronics proprietary digital modulation technology. ECOPACK is a registered trademark of STMicroelectronics. Trademarks and other acknowledgements 53/55 ...
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... Revision history 13 Revision history Table 18. Document revision history Date 12-Dec-2007 54/55 Revision 1 Initial release STA330 Changes ...
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... STA330 Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...