STA330 STMicroelectronics, STA330 Datasheet - Page 17

• Manufacturer Part Number: STA330
• Manufacturer: STMicroelectronics

Specifications of STA330

• Lead Free Status / Rohs Status: Supplier Unconfirmed

STA330
6.1
Functional description
Phase/frequency detector
The phase/frequency detector (PFD) compares the phase difference between the
corresponding rising edges of INFIN and FBCLK, (clock output from the loop frequency
divider) by generating voltage pulses with widths proportional to the input phase error.
Charge pump and loop filter
This block converts the voltage pulses from the phase/frequency detector to current pulses
which charge the loop filter and generate the control voltage for the voltage-controlled
oscillator. The loop filter is placed external to the PLL on pin FILT.
Voltage controlled oscillator
The voltage controlled oscillator (VCO) is the oscillator inside the PLL. It produces a
frequency output (F
Input frequency divider
This frequency divider divides the PLL input clock CLKIN by a factor called the input division
factor (IDF) to generate the PFD input frequency INFIN.
Loop frequency divider
This frequency divider is present within the PLL for dividing F
division factor (LDF). The output of this block is the FBCLK.
Output frequency divider
The PLL output PHI is generated by dividing the F
The divider that divides the F
frequency divider. In the STA330, the ODF is fixed to be divisible by 2 and cannot be
configured.
Lock-detect circuit
The output of this block (the LOCKP signal) is asserted high when the PLL enters the state
of COARSE LOCK in which the output frequency is within ±10% (approximately) of the
desired frequency. The LOCKP signal is refreshed every 32 cycles of the INFIN. The
generated value is based on the result of comparing the number of FBCLK cycles in a
window of 14 INFIN cycles. The different cases generated after comparison are as follows.
"
"
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If LOCKP is already at 0, then in the next refresh cycle LOCKP goes to 1 if the number
of FBCLK cycles in the 14-cycle INFIN window is 13, 14, or 15. Otherwise LOCKP
stays at 0.
If LOCKP is already at 1, then in the next refresh cycle LOCKP goes to 0 if the number
of FBCLK cycles in the 25-cycle INFIN window is less than 11 or higher than 17,
otherwise LOCKP stays at 1.
If LOCKP is already at 1 and CLKIN is lost (no longer present on the input pin), LOCKP
stays at 1. In this case, the PLL is unlocked.
VCO
) proportional to the input control voltage.
VCO
to generate the clock to the core is called the output
VCO
by the output division factor (ODF).
VCO
by a factor called the loop
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PLL