SSTUH32865ET-T NXP Semiconductors, SSTUH32865ET-T Datasheet - Page 14

SSTUH32865ET-T

Manufacturer Part Number
SSTUH32865ET-T
Description
Manufacturer
NXP Semiconductors
Datasheet

Specifications of SSTUH32865ET-T

Logic Family
SSTU
Logical Function
Reg Bfr W/ParityTst
Number Of Elements
1
Number Of Bits
28
Number Of Inputs
28
Number Of Outputs
56
High Level Output Current
-12mA
Low Level Output Current
12mA
Propagation Delay Time
3ns
Operating Supply Voltage (typ)
1.8V
Operating Supply Voltage (max)
1.9V
Operating Supply Voltage (min)
1.7V
Clock-edge Trigger Type
Posit/Negat-Edge
Polarity
Non-Inverting
Technology
CMOS
Frequency (max)
450(Min)MHz
Mounting
Surface Mount
Pin Count
160
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Not Compliant
Philips Semiconductors
9397 750 14136
Product data sheet
Fig 7. Parity logic diagram
Dn
(1) This function holds the error for two cycles. For details, see
CLOCK
PARIN
switches from LOW to
22
D
Q
22
HIGH”.
D
D
Rev. 01 — 11 March 2005
1.8 V high output drive DDR registered buffer with parity
Section 7 “Functional description”
D
RESET FUNCTION
LATCHING AND
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
and
SSTUH32865
(1)
Figure 4 “RESET
002aaa417
QnA
QnB
PTYERR
14 of 28

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