PPC5561MVZ132 Freescale Semiconductor, PPC5561MVZ132 Datasheet

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... The embedded architecture enhancements improve the performance in embedded applications. The core also has additional instructions, including digital signal processing (DSP) instructions, beyond the original Power PC instruction set. © Freescale Semiconductor, Inc., 2008. All rights reserved. Document Number: MPC5561 Rev. 2.0, 27 May 2008 Contents 1 Overview ...

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... FlexRay Protocol Specification 2.0. The FlexRay module uses fault-tolerant, time-triggered events and clock synchronization mechanisms to maintain the global time of the functional nodes. Bus guardian operations are available for each channel in a multi- or redundant-channel configuration. 2 MPC5561 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor ...

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... Speed is the nominal maximum frequency. Max. speed is the maximum speed allowed including frequency modulation (FM). 82 MHz parts allow for 80 MHz system clock + 2% FM; 114 MHz parts allow for 112 MHz system clock + 2% FM; and 135 MHz parts allow for 132 MHz system clock + 2% FM. Freescale Semiconductor M PC 5561 ...

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... DDA DDA DD – V –0.3 5.5 RL – V –5.5 5.5 DDA – V –0.3 0.3 SSA – V –V V DDA DDA DDEH – V –0.3 0 Electrical Specifications, Spec 43a. – V –0.1 0.1 SS – V –0.1 0 –2 2 MAXD I –3 3 MAXA T T 150 –55.0 150.0 STG Freescale Semiconductor Unit ...

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... Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature. 6 Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. Freescale Semiconductor 11 and ...

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... Specifying the local ambient conditions explicitly as the board temperature provides a more precise description of the local ambient conditions that determine the temperature of the device can be obtained from the equation: J × MPC5561 Microcontroller Data Sheet, Rev. 2.0 C/W) 2 Freescale Semiconductor ...

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... T Ψ = thermal characterization parameter ( power dissipation in the package (W) D The thermal characterization parameter is measured in compliance with the JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. Position the thermocouple Freescale Semiconductor × C/W) per JESD51-8 θCA o ...

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... Table 4. EMI Testing Specifications Minimum 0.15 — — operating voltages — DDE — — — MPC5561 Microcontroller Data Sheet, Rev. 2.0 Section 2, “Ordering 1 Typical Maximum Unit — 1000 MHz — f MHz MAX 1.5 — V 3.3 — V 5.0 — — 14 dBuV — Freescale Semiconductor ...

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... RCCTL Voltage differential during power up such that can lag DD33 DDSYN DDEH6 V and V minimums respectively. POR33 POR5 Freescale Semiconductor 1, 2 Table 5. ESD Ratings Symbol R1 C — — — ) and Power-On Reset (POR) RC and POR electrical specifications: Table 6. VRC/POR Electrical Specifications Characteristic ...

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... DD = 2.2 V. VRCCTL Electrical Specification the RESET power supplies is required and during power up, V DDSYN stage turn-on to operate RC leads or lags RC33 to rise until the 1.5 V POR DD Freescale Semiconductor Units 50 V/ms — — — — 500 — ÷ VRCCTL must RC33 ...

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... When powering up the device, V more than the V lag specification listed in DD33 bypass clock mode because the internal versions of PLLCFG[0:1] and RSTCFG are not powered and Freescale Semiconductor have no delta requirement to each other, because the bypass DDSYN to operate within specification. RC Pin Status for Fast Pad Output Driver ...

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... RESET power reach 2.0 V DDSYN RC33 Grounded) RC33 RC33 MPC5561 Microcontroller Data Sheet, Rev. 2.0 can lag V or the RESET power DDSYN lag specification DD33 power supply and the RESET DDSYN V and RESET Power DDSYN V DD Grounded) grounded decreases to less than DD Freescale Semiconductor power DD ...

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... Load capacitance (fast I/O) DSC (SIU_PCR[8: 0b00 = 0b01 = 0b10 = 0b11 24 Input capacitance (digital pins) 25 Input capacitance (analog pins) 26 Input capacitance: (Shared digital and analog pins AN[12]_MA[0]_SDS, AN[13]_MA[1]_SDO, AN[14]_MA[2]_SDI, and AN[15]_FCK) Freescale Semiconductor 1 = –2 2 MPC5561 Microcontroller Data Sheet, Rev. 2.0 Electrical Characteristics = T – Symbol Min Max ...

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... DD_STBY — 70 DD_STBY — 100 DD_STBY — 200 DD_STBY — 1200 DD_STBY — 1500 DD_STBY — 2000 DD_STBY I — (values DD_33 derived from procedure of footnote I — 10 VFLASH I — 15 DDSYN Freescale Semiconductor Unit μA μA μA μA μA μA μA μA μ ...

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... REF differential voltage SSSYN differential voltage RCVSS differential voltage DDF DD 43a differential voltage RC33 DDSYN 44 Analog input differential signal range (with common mode 2.5 V) Freescale Semiconductor MPC5561 Microcontroller Data Sheet, Rev. 2.0 Electrical Characteristics = T – (continued Symbol Min I — DD_A I — ...

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... V. Applies to pad types: pad_fc, pad_sh, and pad_mh. DDE DDEH 125 C. Applies to pad types: pad_a and pad_ae – must be < 0.1 V. SSA0 SSA1 MPC5561 Microcontroller Data Sheet, Rev. 2 – (continued Symbol Min = ( — — have a range of 1.6–3 EBTS = 1. Freescale Semiconductor Max. Unit ο V/ ...

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... Table 10. Table 10. I/O Pad Average DC Current (T Spec Pad Type Symbol 1 2 Slow I DRV_SH 3 4 Freescale Semiconductor worst-case specification to estimate values at STBY Table 9. Istby vs. Junction Tem Tem p (C) Figure 3. I ...

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... I/O segments. The output Table 11 based on the voltage, Table 11. Freescale Semiconductor 17.3 6.5 1.1 3.9 2.8 5.2 8.5 11.0 1.6 2.9 4.2 6.7 2.4 4.4 7.2 9.3 1.3 2.5 3.5 5.7 1 ...

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... These values are estimated from simulation and not tested. Currents apply to output pins for the fast pads only and to input pins for the slow and medium pads only. 2 All loads are lumped. Freescale Semiconductor Pad Average DC Current (T DD33 2 Frequency Load ...

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... DDE5 2 6 — 1.5 — 1.5 Refer to crystal Refer to crystal specification specification (2 × – S_EXTAL — 11 – C PCB_EXTAL (2 × – S_XTAL — 11 – C PCB_XTAL — 750 – –4.0 4.0 –2.0 2.0 Freescale Semiconductor Unit MHz MHz ns kHz MHz μ SYS % f SYS ...

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... Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of (jitter + Cmod). 17 Modulation depth selected must not result in f ÷ RFD sys ico 19 Maximum value for dual controller (1:1) mode is (f Freescale Semiconductor = 3.0–3 0 SSSYN Symbol 15, 16 max: C SYS JITTER 17 C ...

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... The ADCLK ≥ V due to the presence of the sample RL SSA 9. DC Electrical Specifications, spec 35a) can Freescale Semiconductor Unit MHz ADCLK cycles μ Counts Counts Counts Counts Counts Counts mA Counts Counts ...

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... Data retention 2 Blocks with 0–1,000 P/E cycles Blocks with 1,001–100,000 P/E cycles 1 Typical endurance is evaluated at 25 information on the Freescale definition of typical endurance, refer to engineering bulletin EB619 Typical Endurance for Nonvolatile Memory. Freescale Semiconductor Symbol 4 T dwprogram T pprogram T 16kpperase ...

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... V) DDE 4, 5 Rise / Fall Load Drive (ns) (pF 200 200 200 50 260 200 200 200 100 50 125 200 Freescale Semiconductor ...

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... These are worst-case values that are estimated from simulation (not tested). The values in the table are simulated at 1.35–1. 3.0–3 DDE 2 This parameter is supplied for reference and guaranteed by design (not tested). Freescale Semiconductor = 5 DDEH SRC / DSC Out Delay (binary) (ns) ...

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... To calculate the output delay with respect to the system clock, add a maximum of one Rising-edge Falling-edge out delay out delay Figure 4. Pad Output Delay Characteristic = MPC5561 Microcontroller Data Sheet, Rev. 2.0 ÷ Symbol Min. Max. Unit t 10 — t RPW CYC t 2 — t GPW CYC t 10 — t RCSU CYC t 0 — t RCH CYC Freescale Semiconductor ...

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... RESET RSTOUT 3 PLLCFG BOOTCFG RSTCFG WKPCFG Figure 5. Reset and Configuration Pin Timing Freescale Semiconductor 1 MPC5561 Microcontroller Data Sheet, Rev. 2.0 Electrical Characteristics ...

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... JDC t — 3 TCKRISE — TMSS, TDIS — TMSH, TDIH t — 20 TDOV t 0 — TDOI t — 20 TDOHZ t 100 — JCMPPW t 40 — JCMPS t — 50 BSDV t — 50 BSDVZ t — 50 BSDHZ t 50 — BSDST t 50 — BSDHT = 3.0–3.6 V and DDE Freescale Semiconductor Unit ...

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... TCK TMS, TDI TDO TCK JCOMP Freescale Semiconductor Figure 7. JTAG Test Access Port Timing 9 Figure 8. JTAG JCOMP Timing MPC5561 Microcontroller Data Sheet, Rev. 2.0 Electrical Characteristics ...

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... Electrical Characteristics TCK 11 Output signals 12 Output signals Input signals 30 14 Figure 9. JTAG Boundary Scan Timing MPC5561 Microcontroller Data Sheet, Rev. 2 Freescale Semiconductor ...

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... MDO, MSEO, and EVTO data is held valid until the next MCKO low cycle occurs. 4 Limit the maximum frequency to approximately 16 MHz (V specification for JOV JCYC 5 The RDY pin timing is asynchronous to MCKO and is guaranteed by design to function correctly. MCKO MDO MSEO EVTO Freescale Semiconductor Table 21. Nexus Debug Port Timing 1.35–1. and with DSC = 0b10 2.25– ...

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... Electrical Characteristics TCK TMS, TDI TDO Figure 11. Nexus TDI, TMS, TDO Timing MPC5561 Microcontroller Data Sheet, Rev. 2.0 12 Freescale Semiconductor ...

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... WE/BE[0:3] CLKOUT positive edge to output signal valid (output delay) External bus interface CS[0:3] ADDR[8:31] 5 DATA[0:31] 6 BDIP OE RD_WR TA 6 TEA TS 7 WE/BE[0:3] Freescale Semiconductor Table 22. Bus Operation Timing External Bus Frequency Symbol 40 MHz 56 MHz Min. Max. Min. Max. T 24.4 — 17 45% 55% ...

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... V only; EBTS = 1 timings are tested and valid at V DDE Voh_f 3 4 Figure 12. CLKOUT Timing MPC5561 Microcontroller Data Sheet, Rev. 2.0 1 (continued Unit 66 MHz Max. Min. Max. — 5.0 — ns — 1.0 — and with DSC = 0b10 DDE V DDE Freescale Semiconductor Notes = 1.6–3.6 V. ÷ 2 ...

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... CLKOUT 5 Output ÷ DDE bus 5 Output ÷ DDE signal Output signal Freescale Semiconductor 6 6 Figure 13. Synchronous Output Timing MPC5561 Microcontroller Data Sheet, Rev. 2.0 Electrical Characteristics ÷ DDE 5 ÷ DDE 5 6 ÷ DDE 35 ...

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... Applies when IRQ signals are configured for rising-edge or falling-edge events, but not both. 36 ÷ DDE 7 ÷ DDE 7 Figure 14. Synchronous Input Timing Table 23. External Interrupt Timing Symbol t IPWL T IPWH t ICYC = MPC5561 Microcontroller Data Sheet, Rev. 2 Min. Max. Unit 3 — t CYC 3 — t CYC 6 — t CYC Freescale Semiconductor ...

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... This specification does not include the rise and fall times. When calculating the minimum eMIOS pulse width, include the rise and fall times defined in the slew rate control field (SRC) in the pad configuration register (PCR). eMIOS output eMIOS input Freescale Semiconductor 2 3 Figure 15. External Interrupt Timing Table 24. eMIOS Timing ...

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... V DDEH A Freescale Semiconductor Unit — ÷ ...

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... SCK output (CPOL=1) SIN SOUT Figure 17. DSPI Classic SPI Timing—Master, CPHA = 0 PCSx SCK output (CPOL=0) SCK output (CPOL=1) SIN SOUT Figure 18. DSPI Classic SPI Timing—Master, CPHA = 1 Freescale Semiconductor Last data First data Data 12 First data Data Last data 9 ...

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... SCK input (CPOL=1) SOUT SIN Figure 20. DSPI Classic SPI Timing—Slave, CPHA = First data Data Last data 9 10 Data Last data First data 11 5 Data First data 9 10 Data First data MPC5561 Microcontroller Data Sheet, Rev. 2 Last data Last data Freescale Semiconductor ...

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... SIN SOUT Figure 21. DSPI Modified Transfer Format Timing—Master, CPHA = 0 PCSx SCK output (CPOL=0) SCK output (CPOL=1) SIN SOUT Figure 22. DSPI Modified Transfer Format Timing—Master, CPHA = 1 Freescale Semiconductor First data Last data Data 12 11 First data Last data Data ...

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... Figure 24. DSPI Modified Transfer Format Timing—Slave, CPHA = 1 PCSS PCSx First data Data Last data 10 9 Data First data Last data 11 5 First data Data 9 10 First data Data 7 Figure 25. DSPI PCS Strobe (PCSS) Timing MPC5561 Microcontroller Data Sheet, Rev. 2 Last data Last data 8 Freescale Semiconductor ...

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... FCK duty cycle is not 50% when it is generated through the division of the system clock by an odd number. FCK SDS SDO External device data sample at FCK falling-edge SDI EQADC data sample at FCK rising-edge Freescale Semiconductor Symbol Minimum FCK − 6 ...

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... EMIOS EMIOS CNTXA VDDE5 NC VSS EMIOS EMIOS EMIOS EMIOS CNRXA VDDE5 CLKOUT VSS EMIOS EMIOS EMIOS EMIOS PCSC3 PCSC4 VDDE5 Freescale Semiconductor 21 22 VDD33 VSS A VSS VDDE7 B VDDE7 VDD C TCK TDI D TDO TEST E EVTI EVTO F G GPIO SINB H 204 TXDD VPP M N ...

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... MPC5561 324-Pin Package Dimensions The package drawings of the MPC5561 324-pin TEPBGA package are shown in Freescale Semiconductor Figure 28. MPC5561 324 TEPBGA Package MPC5561 Microcontroller Data Sheet, Rev. 2.0 Mechanicals Figure 28. 45 ...

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... Mechanicals Figure 28. MPC5561 324 TEPBGA Package (continued) 46 MPC5561 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor ...

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... PLLCFG[0:1] and RSTCFG are not powered and therefore cannot read the default state when POR negates. V can lag V DD33 V lag specification. This V DD33 requirements when powering down.’ Freescale Semiconductor Description of Changes Table 1: ‘Unless noted in this data sheet, all specifications apply from T Grounded),” then Grounded). VDD33,” changed: must not lag V ...

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... DD and V . DDE DDEH supply to a time period less than the time required to DD Grounded)” Deleted the underscore in ORed_POR to become ORed POR. Description of Changes MPC5561 Microcontroller Data Sheet, Rev. 2.0 Pin Status for Medium / Slow Pads During the Freescale Semiconductor ...

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... Rewrote old footnote 7(new footnote 9) to: Represents the worst-case external transistor BETA measured on a per part basis and calculated as (I • Deleted old footnote 8: ‘Preliminary value. Final specification pending characterization.’ Freescale Semiconductor Description of Changes powered by I/O pads (eTPUB15 and SINB), including the DDEH differential voltage’ ...

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... MPC5561 Microcontroller Data Sheet, Rev. 2 Asserted, Hi-Z. DD33 DD = –2.0 mA):’ OH_S = –1.0 mA.’ OH_S ’ and put ‘0.85 × V DDEH DDEH = 2.0 mA):’ Created a left-justified second line ’ and put ‘0.15 × V DDEH DDEH Freescale Semiconductor ’ on the last ’ on the last ...

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... ICO output and then divide-by-two the RFD to provide the 40 MHz system clock.’ • Spec 21: Changed column 5 from ‘ MHz’ to: ‘150’. • Spec 22: Changed column 4, Max. Value from f dual controller (1:1) mode is (f Freescale Semiconductor Description of Changes values listed in Table 9 ...

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... – the table title Derated Pad AC Specifications: = 132 MHz.’ = 132 MHz.’ SYS = 132 MHz.’ and ‘, and with DSC = 0b10, SRC = 0b11’ SYS MPC5561 Microcontroller Data Sheet, Rev. 2 typical supply voltage using a Freescale Semiconductor ...

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... Table 9 DC Electrical Specifications. On power down, assert RESET before any power supplies fall outside the operating conditions and until the internal POR asserts. Freescale Semiconductor Description of Changes = 132 MHz’, ‘.V and V = 3.0–3.6 V’ and ‘ and CL = 200 pF with SRC = 0b11.’ ...

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... DATA[16:31], TEA, and WE/BE[2:3] signals are not available on the 324 package. 54 Description of Changes and V are limited to 2.25–3.6 V only if EBTS = 0; V DDE2 DDE3 = 4.5–5.5;’ to ‘V = 4.5–5.25;’ DDEH DDEH = 132 MHz.’ MPC5561 Microcontroller Data Sheet, Rev. 2.0 and V have DDE2 DDE3 Freescale Semiconductor ...

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... L1 -> FRBTX, L2 -> PDISNCLK, L3 -> GPIO114, L4 -> PDILINEVALID, L20 -> PCSC5, L21 -> PCSC2, L22 -> PCSC1 • M2 -> IRQ7, M19 -> PCSB2, M20 -> TXDC, M21 -> TXDD • N19 -> RXDC, N21 -> PCSB3 • AB18 -> PCSC3, AB19 -> PCSC4 Freescale Semiconductor Description of Changes = 4.5–5.5;’ to ‘V = 4.5–5.25;’ DDEH DDEH = 132 MHz. . .’ ...

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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...