PPC5561MVZ132 Freescale Semiconductor, PPC5561MVZ132 Datasheet - Page 55

• Manufacturer Part Number: PPC5561MVZ132
• Manufacturer: Freescale Semiconductor

Specifications of PPC5561MVZ132

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Freescale Semiconductor
Table 24
Table 25
Table 26
Figure 27
Location
eMIOS Timing:
DSPI Timing:
EQADC SSI Timing Characteristics:
MPC5561 324 PBGA Pinouts:
• Footnote 1, changed ‘V
• Deleted (MTS) from the heading, table, and footnotes.
• Footnote 1: Deleted ‘. . .f
• Added Footnote 2: ‘This specification does not include the rise and fall times. When calculating the minimum
• Footnote 1, changed ‘V
• Table Title: Added footnote that reads: Speed is the nominal maximum frequency. Max. speed is the maximum
• Footnote 1, changed ‘V
• Deleted from table title ‘(Pads at 3.3 V or 5.0 V)’
• Deleted 1st line in table ‘CLOAD = 25 pF on all outputs. Pad drive strength set to maximum.’
• Spec 1: FCK frequency -- removed.
• Combined footnotes 1 and 2, and moved the new footnote to Spec 2. Moved old footnote 3 to Spec 2.
• Footnote 1, deleted ‘V
• Footnote 2: added ‘cycle’ after ‘duty’ to read: FCK duty cycle is not 50% when . . . .
• Changed ball labels on the 324 PBGA to show only signals available on the device:
• C1 -> PSCS3, C2 -> PCSC4,
• D1 -> PCSC1, D2 -> PCSC2, D3 -> IRQ14
• E1 -> IRQ12, E2 -> IRQ15, E3 -> IRQ13, E4 -> IRQ9
• F1 -> IRQ11, F2 -> IRQ10, F3 -> PDI_DATA6, F4 -> PDI_DATA7
• G1 -> IRQ8, G2 -> PDI_DATA8, G3 -> PCSB4, G4 -> PCSB3
• H1 -> PDI_DATA5, H2 -> PCSB5, H3 -> PDICHSEL2
• J1 -> PCSB1, J2 -> PDI_DATA0, J3 -> FRN_RX, J4 -> PDICHSEL1
• K1 -> PDICHSEL0, K2 -> GPIO121, K3 -> PDI_FRAME_VALID, K4 -> FRBTXEN, K19 -> RXDD
• L1 -> FRBTX, L2 -> PDISNCLK, L3 -> GPIO114, L4 -> PDILINEVALID, L20 -> PCSC5, L21 -> PCSC2,
• M2 -> IRQ7, M19 -> PCSB2, M20 -> TXDC, M21 -> TXDD
• N19 -> RXDC, N21 -> PCSB3
• AB18 -> PCSC3, AB19 -> PCSC4
with SRC = 0b11.’
eMIOS pulse width, include the rise and fall times defined in the slew rate control fields (SRC) of the pad
configuration registers (PCR).’
speed allowed including frequency modulation (FM). 82 MHz parts allow for 80 MHz system clock + 2% FM;
114 MHz parts allow for 112 MHz system clock + 2% FM, and 135 MHz parts allow for 132 MHz system clock +
2% FM.
Changed ‘CL = 50 pF’ to ‘CL = 25 pF.’
L22 -> PCSC1
Table 29. Information Changed Between Rev. 1.0 and Rev. 2.0 (continued)
DD
DDEH
DDEH
DDEH
MPC5561 Microcontroller Data Sheet, Rev. 2.0
SYS
= 1.35–1.65 V’ and ‘V
= 132 MHz. . .’, ‘. . .V
= 4.5–5.5;’ to ‘V
= 4.5–5.5;’ to ‘V
= 4.5–5.5;’ to ‘V
Description of Changes
DDEH
DDEH
DDEH
DD33
DD33
= 4.5–5.25;’
= 4.5–5.25;’
= 4.5–5.25;’
and V
and V
DDSYN
DDSYN
Revision History for the MPC5561 Data Sheet
= 3.0–3.6V.’
= 3.0–3.6 V. . .’ and ‘ . . .and CL = 200 pF
55