EVAL-ADV7314EB Analog Devices Inc, EVAL-ADV7314EB Datasheet - Page 13

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EVAL-ADV7314EB

Manufacturer Part Number
EVAL-ADV7314EB
Description
Manufacturer
Analog Devices Inc
Datasheet

Specifications of EVAL-ADV7314EB

Lead Free Status / Rohs Status
Not Compliant
REV. 0
S9–S0/Y9–Y0*
P_HSYNC
P_VSYNC
P_BLANK
a = 32 CLK CYCLES FOR 525p
a = 24 CLK CYCLES FOR 625p
AS RECOMMENDED BY STANDARD
b(MIN) = 244 CLK CYCLES FOR 525p
b(MIN) = 264 CLK CYCLES FOR 625p
S_HSYNC
S_VSYNC
S_BLANK
*SELECTED BY ADDRESS 0x01 BIT 7
Y9–Y0
SCLK
SDA
Figure 14. PS 4:2:2 1 10-Bit Interleaved Input Timing Diagram
PAL = 24 CLKCYCLES
NTSC = 32 CLKCYCLES
t
3
Figure 15. SD Timing Input for Timing Mode 1
a
t
6
t
2
Figure 16. MPU Port Timing Diagram
t
7
t
1
t
5
–13–
b
t
4
t
3
PAL = 24 CLK CYCLES
NTSC = 32 CLK CYCLES
Cb
t
8
Cb
Y
Y
Cr
Cr
Y
Y
ADV7314