EVAL-ADV7314EB Analog Devices Inc, EVAL-ADV7314EB Datasheet - Page 32

• Manufacturer Part Number: EVAL-ADV7314EB
• Manufacturer: Analog Devices Inc

Specifications of EVAL-ADV7314EB

• Lead Free Status / Rohs Status: Not Compliant

ADV7314
Simultaneous Standard Definition and
Progressive Scan or HDTV
Address [01h]: Input Mode 011(SD 40-Bit, PS 20-Bit) or
101 (SH and HD, SD Oversampled), 110 (SD and HD, HD
Oversampled)
YCrCb PS, HDTV, or any other HD data must be input in
4:2:2 format. In 4:2:2 input mode, the HD Y data is input on
Pins Y9–Y0 and the HD CrCb data on C9–C0.
If PS 4:2:2 data is interleaved onto a single 10-bit bus, Y9–Y0 are
used for the input port. The input data is to be input at 27 MHz
with the data clocked on the rising and falling edge of the input
clock. The input mode register at Address 01h is set accordingly.
If the YCrCb data does not conform to SMPTE 293M (525p),
ITU-R BT.1358M (625p), SMPTE 274M (1080i), SMPTE
296M (720p), or BTA T-1004, the Async Timing mode must
be used.
The 8-bit or 10-bit standard definition data must be compliant
to ITU-R BT.601/656 in 4:2:2 format.
Standard definition data is input on Pins S9–S0, with S0 being the
LSB. Using 8-bit input format, the data is input on Pins S9–S2.
The clock input for SD must be input on CLKIN_A, and the
clock input for HD must be input on CLKIN_B.
Synchronization signals are optional. SD syncs are input on pins
S_VSYNC, S_ HSYNC, and S_BLANK.
HD syncs are input on Pins P_VSYNC, P_ HSYNC, P_BLANK.
If in simultaneous SD/HD input mode, the two clock phases
differ by less than 9.25 ns or more than 27.75 ns, the CLOCK
Figure 24. Simultaneous HD and SD Input
Figure 23. Simultaneous PS and SD Input
INTERLACED TO
PROGRESSIVE
DECODER
DECODER
DECODER
MPEG2
SDTV
HDTV
YCrCb
1080 i
720 p
YCrC b
CrCb
Y
74.25MHz
27MHz
CrCb
27MHz
Y
27MHz
10
10
10
3
10
10
10
3
3
3
S_VSYNC
S_HSYNC
S_BLANK
CLKIN_A
S[9:0]
C[9:0]
Y[9:0]
P_VSYNC
P_HSYNC
P_BLANK
CLKIN_B
S_VSYNC
S_HSYNC
S_BLANK
CLKIN_A
S[9:0]
C[9:0]
Y[9:0]
P_VSYNC
P_HSYNC
P_BLANK
CLKIN_B
ADV7314
ADV7314
–32–
ALIGN bit [Address 01h, Bit 3] must be set accordingly. If the
application uses the same clock source for both SD and PS, the
CLOCK ALIGN bit must be set since the phase difference
between both inputs is less than 9.25 ns.
Progressive Scan at 27 MHz (Dual Edge) or 54 MHz
Address [01h]: Input Mode 100 OR 111, Respectively
YCrCb progressive scan data can be input at 27 MHz or 54
MHz. The input data is interleaved onto a single 8-/10-bit bus
and is input on Pins Y9–Y0. When a 27 MHz clock is supplied,
the data is clocked in on the rising and falling edge of the input
clock and CLOCK EDGE [Address 01h, Bit 1] must be set
accordingly.
The following figures show the possible conditions. (a) Cb data
on the rising edge and (b) Y data on the rising edge.
With a 54 MHz clock, the data is latched on the every rising edge.
CLKIN_A
CLKIN_B
PIXEL INPUT
CLKIN_B
CLKIN_B
Y9–Y0
Y9–Y0
Figure 26a. Clock Edge Address 01h, Bit 1
Should Be Set to 0
Figure 26b. Clock Edge Address 01h, Bit 1
Should Be Set to 1
Figure 26c. Input Sequence in PS Bit Interleaved
Mode, EAV/SAV Followed by Cb0 Data
CLKIN
DATA
Figure 25. Clock Phase with Two Input Clocks
Figure 27. 1
3FF
3FF
t
t
DELAY
DELAY
PROGRESSIVE
DECODER
INTERLACED
3FF
MPEG2
YCrCb
TO
00
00
9.25ns OR
27.75ns
00
10-Bit PS at 27 MHz or 54 MHz
00
00
27MHz OR
YCrCb
00
54MHz
XY
XY
10
3
XY
Cb0
Y0
CLKIN_A
Y[9:0]
P_VSYNC
P_HSYNC
P_BLANK
ADV7314
Cb0
Cb0
Y0
Y0
Cr0
Y1
Cr0
REV. 0
Cr0
Y1
Y1