EVAL-ADV7314EB Analog Devices Inc, EVAL-ADV7314EB Datasheet - Page 58

• Manufacturer Part Number: EVAL-ADV7314EB
• Manufacturer: Analog Devices Inc

Specifications of EVAL-ADV7314EB

• Lead Free Status / Rohs Status: Not Compliant

ADV7314
PC BOARD LAYOUT CONSIDERATIONS
The ADV7314 is optimally designed for lowest noise perfor-
mance, for both radiated and conducted noise. To complement
the excellent noise performance of the ADV7314, it is impera-
tive that great care be given to the PC board layout.
The layout should be optimized for lowest noise on the ADV7314
power and ground lines. This can be achieved by shielding the
digital inputs and providing good decoupling. The lead length
between groups of V
V
minimized inductive ringing.
It is recommended that a 4-layer printed circuit board is used
with power and ground planes separating the layer of the signal
carrying traces of the components and solder side layer. Com-
ponent placement should be carefully considered in order to
separate noisy circuits, such as crystal clocks, high speed logic
circuitry, and analog circuitry.
There should be a separate analog ground plane and a separate
digital ground plane.
Power planes should encompass a digital power plane and an
analog power plane. The analog power plane should contain the
DACs and all associated circuitry, V
power plane should contain all logic circuitry.
The analog and digital power planes should be individually con-
nected to the common power plane at one single point through a
suitable filtering device, such as a ferrite bead.
DAC output traces on a PCB should be treated as transmission
lines. It is recommended that the DACs be placed as close as
possible to the output connector, with the analog output traces
being as short as possible (less than 3 inches). The DAC termi-
nation resistors should be placed as close as possible to the
DAC outputs and should overlay the PCB’s ground plane. As
well as minimizing reflections, short analog output traces will
reduce noise pickup due to neighboring digital circuitry.
To avoid crosstalk between the DAC outputs, it is recommended
to leave as much space as possible between the tracks of the
individual DAC output pins. The addition of ground tracks
between outputs is also recommended.
DD_IO
and GND_IO pins should be kept as short as possible to
AA
and AGND, V
REF
DD
circuitry. The digital
and DGND, and
–58–
Supply Decoupling
Noise on the analog power plane can be further reduced by the
use of decoupling capacitors.
Optimum performance is achieved by the use of 10 nF and
0.1 mF ceramic capacitors. Each of group of V
pins should be individually decoupled to ground. This should
be done by placing the capacitors as close as possible to the
device with the capacitor leads as short as possible, thus mini-
mizing lead inductance.
A 1 mF tantalum capacitor is recommended across the V
in addition to a 10 nF ceramic capacitor. See Figure 60.
Digital Signal Interconnect
The digital signal lines should be isolated as much as possible
from the analog outputs and other analog circuitry. Digital
signal lines should not overlay the analog power plane.
Due to the high clock rates used, long clock lines to the ADV7314
should be avoided to minimize noise pickup.
Any active pull-up termination resistors for the digital inputs
should be connected to the digital power plane and not to the
analog power plane.
Analog Signal Interconnect
The ADV7314 should be located as close as possible to the
output connectors, thus minimizing noise pickup and reflections
due to impedance mismatch.
For optimum performance, the analog outputs should each be
source and load terminated, as shown in Figure 60. The termi-
nation resistors should be as close as possible to the ADV7314
to minimize reflections.
For optimum performance, it is recommended that all decoupling
and external components relating to the ADV7314 be located on
the same side of the PCB and as close as possible to the ADV7314.
Any unused inputs should be tied to ground.
AA
, V
DD
, or V
AA
REV. 0
supply
DD_IO